| Message ID | 1649938766-6768-5-git-send-email-quic_sbillaka@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for the eDP panel over aux_bus | expand |
Hi, On Thu, Apr 14, 2022 at 5:20 AM Sankeerth Billakanti <quic_sbillaka@quicinc.com> wrote: > > The eDP controller does not have a reliable way keep panel > powered on to read the sink capabilities. So, the controller > driver cannot validate if a mode can be supported by the > source. We will rely on the panel driver to populate only > the supported modes for now. > > Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com> > --- > drivers/gpu/drm/msm/dp/dp_display.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c > index c7277f0..0f18a16 100644 > --- a/drivers/gpu/drm/msm/dp/dp_display.c > +++ b/drivers/gpu/drm/msm/dp/dp_display.c > @@ -998,6 +998,14 @@ enum drm_mode_status dp_bridge_mode_valid(struct drm_bridge *bridge, > return -EINVAL; > } > > + /* > + * The eDP controller currently does not have a reliable way of > + * enabling panel power to read sink capabilities. So, we rely > + * on the panel driver to populate only supported modes for now. > + */ > + if (dp->is_edp) > + return MODE_OK; As discussed out-of-band, I agree that this is the right thing for now and making this assumption won't break anything. In general the set of eDP panels is known ahead of time it's fairly unlikely someone would set things up so that a panel couldn't use the mode it was reporting. Longer term we should figure out a way to solve this but it doesn't have to be today. To properly implement mode_valid() we've got to combine knowledge from the panel (mostly rates supported and number of lanes supported) with the controller (rates supported, number of lanes supported/hooked up on this board). In any case: Reviewed-by: Douglas Anderson <dianders@chromium.org>
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index c7277f0..0f18a16 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -998,6 +998,14 @@ enum drm_mode_status dp_bridge_mode_valid(struct drm_bridge *bridge, return -EINVAL; } + /* + * The eDP controller currently does not have a reliable way of + * enabling panel power to read sink capabilities. So, we rely + * on the panel driver to populate only supported modes for now. + */ + if (dp->is_edp) + return MODE_OK; + if ((dp->max_pclk_khz <= 0) || (dp->max_pclk_khz > DP_MAX_PIXEL_CLK_KHZ) || (mode->clock > dp->max_pclk_khz))
The eDP controller does not have a reliable way keep panel powered on to read the sink capabilities. So, the controller driver cannot validate if a mode can be supported by the source. We will rely on the panel driver to populate only the supported modes for now. Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com> --- drivers/gpu/drm/msm/dp/dp_display.c | 8 ++++++++ 1 file changed, 8 insertions(+)