| Message ID | 20220420142432.248565-1-luca.ceresoli@bootlin.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] pinctrl: rockchip: fix RK3308 pinmux bits | expand |
Am Mittwoch, 20. April 2022, 16:24:31 CEST schrieb Luca Ceresoli: > Some of the pinmuxing bits described in rk3308_mux_recalced_data are wrong, > pointing to non-existing registers. > > Fix the entire table. > > Also add a comment in front of each entry with the same string that appears > in the datasheet to make the table easier to compare with the docs. > > This fix has been tested on real hardware for the gpio3b3_sel entry. > > Fixes: 7825aeb7b208 ("pinctrl: rockchip: add rk3308 SoC support") > Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Thanks for walking through the datasheet for the fixes :-) > --- > drivers/pinctrl/pinctrl-rockchip.c | 45 ++++++++++++++++++++---------- > 1 file changed, 30 insertions(+), 15 deletions(-) > > diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c > index a1b598b86aa9..65fa305b5f59 100644 > --- a/drivers/pinctrl/pinctrl-rockchip.c > +++ b/drivers/pinctrl/pinctrl-rockchip.c > @@ -457,95 +457,110 @@ static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { > > static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { > { > + /* gpio1b6_sel */ > .num = 1, > .pin = 14, > .reg = 0x28, > .bit = 12, > .mask = 0xf > }, { > + /* gpio1b7_sel */ > .num = 1, > .pin = 15, > .reg = 0x2c, > .bit = 0, > .mask = 0x3 > }, { > + /* gpio1c2_sel */ > .num = 1, > .pin = 18, > .reg = 0x30, > .bit = 4, > .mask = 0xf > }, { > + /* gpio1c3_sel */ > .num = 1, > .pin = 19, > .reg = 0x30, > .bit = 8, > .mask = 0xf > }, { > + /* gpio1c4_sel */ > .num = 1, > .pin = 20, > .reg = 0x30, > .bit = 12, > .mask = 0xf > }, { > + /* gpio1c5_sel */ > .num = 1, > .pin = 21, > .reg = 0x34, > .bit = 0, > .mask = 0xf > }, { > + /* gpio1c6_sel */ > .num = 1, > .pin = 22, > .reg = 0x34, > .bit = 4, > .mask = 0xf > }, { > + /* gpio1c7_sel */ > .num = 1, > .pin = 23, > .reg = 0x34, > .bit = 8, > .mask = 0xf > }, { > + /* gpio3b4_sel */ > .num = 3, > .pin = 12, > .reg = 0x68, > .bit = 8, > .mask = 0xf > }, { > + /* gpio3b5_sel */ > .num = 3, > .pin = 13, > .reg = 0x68, > .bit = 12, > .mask = 0xf > }, { > + /* gpio2a2_sel */ > .num = 2, > .pin = 2, > - .reg = 0x608, > - .bit = 0, > - .mask = 0x7 > + .reg = 0x40, > + .bit = 4, > + .mask = 0x3 > }, { > + /* gpio2a3_sel */ > .num = 2, > .pin = 3, > - .reg = 0x608, > - .bit = 4, > - .mask = 0x7 > + .reg = 0x40, > + .bit = 6, > + .mask = 0x3 > }, { > + /* gpio2c0_sel */ > .num = 2, > .pin = 16, > - .reg = 0x610, > - .bit = 8, > - .mask = 0x7 > + .reg = 0x50, > + .bit = 0, > + .mask = 0x3 > }, { > + /* gpio3b2_sel */ > .num = 3, > .pin = 10, > - .reg = 0x610, > - .bit = 0, > - .mask = 0x7 > + .reg = 0x68, > + .bit = 4, > + .mask = 0x3 > }, { > + /* gpio3b3_sel */ > .num = 3, > .pin = 11, > - .reg = 0x610, > - .bit = 4, > - .mask = 0x7 > + .reg = 0x68, > + .bit = 6, > + .mask = 0x3 > }, > }; > >
On Wed, Apr 20, 2022 at 4:24 PM Luca Ceresoli <luca.ceresoli@bootlin.com> wrote: > Some of the pinmuxing bits described in rk3308_mux_recalced_data are wrong, > pointing to non-existing registers. > > Fix the entire table. Patches 1 + 2 applied for fixes! Yours, Linus Walleij
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index a1b598b86aa9..65fa305b5f59 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -457,95 +457,110 @@ static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { { + /* gpio1b6_sel */ .num = 1, .pin = 14, .reg = 0x28, .bit = 12, .mask = 0xf }, { + /* gpio1b7_sel */ .num = 1, .pin = 15, .reg = 0x2c, .bit = 0, .mask = 0x3 }, { + /* gpio1c2_sel */ .num = 1, .pin = 18, .reg = 0x30, .bit = 4, .mask = 0xf }, { + /* gpio1c3_sel */ .num = 1, .pin = 19, .reg = 0x30, .bit = 8, .mask = 0xf }, { + /* gpio1c4_sel */ .num = 1, .pin = 20, .reg = 0x30, .bit = 12, .mask = 0xf }, { + /* gpio1c5_sel */ .num = 1, .pin = 21, .reg = 0x34, .bit = 0, .mask = 0xf }, { + /* gpio1c6_sel */ .num = 1, .pin = 22, .reg = 0x34, .bit = 4, .mask = 0xf }, { + /* gpio1c7_sel */ .num = 1, .pin = 23, .reg = 0x34, .bit = 8, .mask = 0xf }, { + /* gpio3b4_sel */ .num = 3, .pin = 12, .reg = 0x68, .bit = 8, .mask = 0xf }, { + /* gpio3b5_sel */ .num = 3, .pin = 13, .reg = 0x68, .bit = 12, .mask = 0xf }, { + /* gpio2a2_sel */ .num = 2, .pin = 2, - .reg = 0x608, - .bit = 0, - .mask = 0x7 + .reg = 0x40, + .bit = 4, + .mask = 0x3 }, { + /* gpio2a3_sel */ .num = 2, .pin = 3, - .reg = 0x608, - .bit = 4, - .mask = 0x7 + .reg = 0x40, + .bit = 6, + .mask = 0x3 }, { + /* gpio2c0_sel */ .num = 2, .pin = 16, - .reg = 0x610, - .bit = 8, - .mask = 0x7 + .reg = 0x50, + .bit = 0, + .mask = 0x3 }, { + /* gpio3b2_sel */ .num = 3, .pin = 10, - .reg = 0x610, - .bit = 0, - .mask = 0x7 + .reg = 0x68, + .bit = 4, + .mask = 0x3 }, { + /* gpio3b3_sel */ .num = 3, .pin = 11, - .reg = 0x610, - .bit = 4, - .mask = 0x7 + .reg = 0x68, + .bit = 6, + .mask = 0x3 }, };
Some of the pinmuxing bits described in rk3308_mux_recalced_data are wrong, pointing to non-existing registers. Fix the entire table. Also add a comment in front of each entry with the same string that appears in the datasheet to make the table easier to compare with the docs. This fix has been tested on real hardware for the gpio3b3_sel entry. Fixes: 7825aeb7b208 ("pinctrl: rockchip: add rk3308 SoC support") Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> --- drivers/pinctrl/pinctrl-rockchip.c | 45 ++++++++++++++++++++---------- 1 file changed, 30 insertions(+), 15 deletions(-)