| Message ID | 165040157111.1399644.6123821125319995316.stgit@bmoger-ubuntu (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/2] x86/cpufeatures: Add virtual TSC_AUX feature bit | expand |
On Tue, Apr 19, 2022 at 03:53:52PM -0500, Babu Moger wrote: > The TSC_AUX Virtualization feature allows AMD SEV-ES guests to securely use > TSC_AUX (auxiliary time stamp counter data) MSR in RDTSCP and RDPID > instructions. > > The TSC_AUX MSR is typically initialized to APIC ID or another unique > identifier so that software can quickly associate returned TSC value > with the logical processor. > > Add the feature bit and also include it in the kvm for detection. > > Signed-off-by: Babu Moger <babu.moger@amd.com> > Acked-by: Borislav Petkov <bp@suse.de> > --- > v2: > Fixed the text(commented by Boris). > Added Acked-by from Boris. > > v1: > https://lore.kernel.org/kvm/164937947020.1047063.14919887750944564032.stgit@bmoger-ubuntu/ > > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/kvm/cpuid.c | 2 +- > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 73e643ae94b6..1bc66a17a95a 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -405,6 +405,7 @@ > #define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualization */ > #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is supported */ > #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */ > +#define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* Virtual TSC_AUX */ I forgot from the last time: nothing is going to use that bit in userspace so make that #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */ please. Thx.
On 4/20/22 06:43, Borislav Petkov wrote: > On Tue, Apr 19, 2022 at 03:53:52PM -0500, Babu Moger wrote: >> The TSC_AUX Virtualization feature allows AMD SEV-ES guests to securely use >> TSC_AUX (auxiliary time stamp counter data) MSR in RDTSCP and RDPID >> instructions. >> >> The TSC_AUX MSR is typically initialized to APIC ID or another unique >> identifier so that software can quickly associate returned TSC value >> with the logical processor. >> >> Add the feature bit and also include it in the kvm for detection. >> >> Signed-off-by: Babu Moger <babu.moger@amd.com> >> Acked-by: Borislav Petkov <bp@suse.de> >> --- >> v2: >> Fixed the text(commented by Boris). >> Added Acked-by from Boris. >> >> v1: >> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fkvm%2F164937947020.1047063.14919887750944564032.stgit%40bmoger-ubuntu%2F&data=05%7C01%7Cbabu.moger%40amd.com%7Cf826192970c549ae73af08da22c2ff93%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637860518176768607%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=fExIt5ghvuew%2BXKzGyixye2%2BLQncv91274nt8I0NXbY%3D&reserved=0 >> >> arch/x86/include/asm/cpufeatures.h | 1 + >> arch/x86/kvm/cpuid.c | 2 +- >> 2 files changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h >> index 73e643ae94b6..1bc66a17a95a 100644 >> --- a/arch/x86/include/asm/cpufeatures.h >> +++ b/arch/x86/include/asm/cpufeatures.h >> @@ -405,6 +405,7 @@ >> #define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualization */ >> #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is supported */ >> #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */ >> +#define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* Virtual TSC_AUX */ > I forgot from the last time: nothing is going to use that bit in > userspace so make that > > #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */ Ok. Sure. Thanks > > please. > > Thx. >
On 4/19/22 22:53, Babu Moger wrote: > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index b24ca7f4ed7c..99a4c078b397 100644 > --- a/arch/x86/kvm/cpuid.c > +++ b/arch/x86/kvm/cpuid.c > @@ -674,7 +674,7 @@ void kvm_set_cpu_caps(void) > > kvm_cpu_cap_mask(CPUID_8000_001F_EAX, > 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) | > - F(SME_COHERENT)); > + F(V_TSC_AUX) | F(SME_COHERENT)); > > kvm_cpu_cap_mask(CPUID_C000_0001_EDX, > F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | Not needed, since V_TSC_AUX is not exposed to guests. I made the changes and queued both patches. Paolo
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 73e643ae94b6..1bc66a17a95a 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -405,6 +405,7 @@ #define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualization */ #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is supported */ #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */ +#define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* Virtual TSC_AUX */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ /* diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index b24ca7f4ed7c..99a4c078b397 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -674,7 +674,7 @@ void kvm_set_cpu_caps(void) kvm_cpu_cap_mask(CPUID_8000_001F_EAX, 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) | - F(SME_COHERENT)); + F(V_TSC_AUX) | F(SME_COHERENT)); kvm_cpu_cap_mask(CPUID_C000_0001_EDX, F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |