| Message ID | 20220414122250.158113-11-clement.leger@bootlin.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | add support for Renesas RZ/N1 ethernet subsystem devices | expand |
Hi Clément, On Thu, Apr 14, 2022 at 2:24 PM Clément Léger <clement.leger@bootlin.com> wrote: > RZ/N1 SoC includes two MAC named GMACx that are compatible with the > "snps,dwmac" driver. GMAC1 is connected directly to the MII converter > port 1. GMAC2 however can be used as the MAC for the switch CPU > management port or can be muxed to be connected directly to the MII > converter port 2. This commit add description for the GMAC2 which will > be used by the switch description. > > Signed-off-by: Clément Léger <clement.leger@bootlin.com> Thanks for your patch! > --- a/arch/arm/boot/dts/r9a06g032.dtsi > +++ b/arch/arm/boot/dts/r9a06g032.dtsi > @@ -200,6 +200,23 @@ nand_controller: nand-controller@40102000 { > status = "disabled"; > }; > > + gmac2: ethernet@44002000 { > + compatible = "snps,dwmac-3.72a", "snps,dwmac"; "make dtbs_check": arch/arm/boot/dts/r9a06g032-rzn1d400-db.dtb:0:0: /soc/ethernet@44002000: failed to match any schema with compatible: ['snps,dwmac-3.72a', 'snps,dwmac'] > + reg = <0x44002000 0x2000>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "macirq", "eth_lpi", "eth_wake_irq"; arch/arm/boot/dts/r9a06g032-rzn1d400-db.dtb: ethernet@44002000: interrupt-names:1: 'eth_wake_irq' was expected arch/arm/boot/dts/r9a06g032-rzn1d400-db.dtb: ethernet@44002000: interrupt-names:2: 'eth_lpi' was expected From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml > + clock-names = "stmmaceth"; > + clocks = <&sysctrl R9A06G032_HCLK_GMAC1>; > + snps,multicast-filter-bins = <256>; > + snps,perfect-filter-entries = <128>; > + tx-fifo-depth = <2048>; > + rx-fifo-depth = <4096>; > + status = "disabled"; > + }; > + > eth_miic: eth-miic@44030000 { > compatible = "renesas,rzn1-miic"; > #address-cells = <1>; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index fd174df268e8..9be55957b8e5 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -200,6 +200,23 @@ nand_controller: nand-controller@40102000 { status = "disabled"; }; + gmac2: ethernet@44002000 { + compatible = "snps,dwmac-3.72a", "snps,dwmac"; + reg = <0x44002000 0x2000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_lpi", "eth_wake_irq"; + clock-names = "stmmaceth"; + clocks = <&sysctrl R9A06G032_HCLK_GMAC1>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <2048>; + rx-fifo-depth = <4096>; + status = "disabled"; + }; + eth_miic: eth-miic@44030000 { compatible = "renesas,rzn1-miic"; #address-cells = <1>;
RZ/N1 SoC includes two MAC named GMACx that are compatible with the "snps,dwmac" driver. GMAC1 is connected directly to the MII converter port 1. GMAC2 however can be used as the MAC for the switch CPU management port or can be muxed to be connected directly to the MII converter port 2. This commit add description for the GMAC2 which will be used by the switch description. Signed-off-by: Clément Léger <clement.leger@bootlin.com> --- arch/arm/boot/dts/r9a06g032.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)