[v3,1/4] dt-bindings: display: Document Renesas RZ/G2L DU bindings

Commit Message

Biju Das April 21, 2022, 4:31 p.m. UTC

The RZ/G2L LCD controller is composed of Frame Compression Processor
(FCPVD), Video Signal Processor (VSPD), and Display Unit (DU).

The DU module supports the following hardware features
− Display Parallel Interface (DPI) and MIPI LINK Video Interface
− Display timing master
− Generates video timings
− Selecting the polarity of output DCLK, HSYNC, VSYNC, and DE
− Supports Progressive
− Input data format (from VSPD): RGB888, RGB666
− Output data format: same as Input data format
− Supporting Full HD (1920 pixels x 1080 lines) for MIPI-DSI Output
− Supporting WXGA (1280 pixels x 800 lines) for Parallel Output

This patch document DU module found on RZ/G2L LCDC.

Signed-off-by: Biju Das <[e-mail]>
---
 v3: New patch
---
 .../bindings/display/renesas,rzg2l-du.yaml    | 159 ++++++++++++++++++
 1 file changed, 159 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml

Comments

Geert Uytterhoeven April 22, 2022, 7:53 a.m. UTC | #1

Hi Biju,

On Thu, Apr 21, 2022 at 6:31 PM Biju Das <[e-mail]> wrote:
> The RZ/G2L LCD controller is composed of Frame Compression Processor
> (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU).
>
> The DU module supports the following hardware features
> − Display Parallel Interface (DPI) and MIPI LINK Video Interface
> − Display timing master
> − Generates video timings
> − Selecting the polarity of output DCLK, HSYNC, VSYNC, and DE
> − Supports Progressive
> − Input data format (from VSPD): RGB888, RGB666
> − Output data format: same as Input data format
> − Supporting Full HD (1920 pixels x 1080 lines) for MIPI-DSI Output
> − Supporting WXGA (1280 pixels x 800 lines) for Parallel Output
>
> This patch document DU module found on RZ/G2L LCDC.
>
> Signed-off-by: Biju Das <[e-mail]>

Thanks for your patch!

> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> @@ -0,0 +1,159 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G2L Display Unit (DU)
> +
> +maintainers:
> +  - Laurent Pinchart <[e-mail]>
> +  - Biju Das <[e-mail]>
> +
> +description: |
> +  These DT bindings describe the Display Unit embedded in the Renesas RZ/G2L
> +  and RZ/V2L SoCs.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - renesas,du-r9a07g044c # for RZ/G2LC compatible DU
> +      - renesas,du-r9a07g044l # for RZ/G2L compatible DU

Please use the format "<manuf>,<soc>-<modulo>" for new bindings.

I thought there was no need to differentiate RZ/G2LC and RZ/G2L, as
the only difference is a wiring difference due to the limited number
of pins on the RZ/G2LC package, as per your confirmation[1]?
Hence please just use "renesas,r9a07g044-du".

Do you want a family-specific compatible value ("rzg2l-"), as this
IP block is shared by (at least) RZ/GL(C), RZ/V2L, and RZ/G2UL?

> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - renesas,du-r9a07g044c
> +    then:
> +      properties:
> +        ports:
> +          properties:
> +            port@0:
> +              description: DSI 0
> +          required:
> +            - port@0
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - renesas,du-r9a07g044l
> +    then:
> +      properties:
> +        ports:
> +          properties:
> +            port@0:
> +              description: DPAD 0
> +            port@1:
> +              description: DSI 0
> +          required:
> +            - port@0
> +            - port@1

Having different port numbers for the common DSI0 output indeed
complicates matters ;-)

[1] https://lore.kernel.org/r/[e-mail]/

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [e-mail]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Biju Das April 22, 2022, 8:10 a.m. UTC | #2

Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v3 1/4] dt-bindings: display: Document Renesas RZ/G2L
> DU bindings
> 
> Hi Biju,
> 
> On Thu, Apr 21, 2022 at 6:31 PM Biju Das <[e-mail]>
> wrote:
> > The RZ/G2L LCD controller is composed of Frame Compression Processor
> > (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU).
> >
> > The DU module supports the following hardware features − Display
> > Parallel Interface (DPI) and MIPI LINK Video Interface − Display
> > timing master − Generates video timings − Selecting the polarity of
> > output DCLK, HSYNC, VSYNC, and DE − Supports Progressive − Input data
> > format (from VSPD): RGB888, RGB666 − Output data format: same as Input
> > data format − Supporting Full HD (1920 pixels x 1080 lines) for
> > MIPI-DSI Output − Supporting WXGA (1280 pixels x 800 lines) for
> > Parallel Output
> >
> > This patch document DU module found on RZ/G2L LCDC.
> >
> > Signed-off-by: Biju Das <[e-mail]>
> 
> Thanks for your patch!
> 
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> > @@ -0,0 +1,159 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +
> > +title: Renesas RZ/G2L Display Unit (DU)
> > +
> > +maintainers:
> > +  - Laurent Pinchart <[e-mail]>
> > +  - Biju Das <[e-mail]>
> > +
> > +description: |
> > +  These DT bindings describe the Display Unit embedded in the Renesas
> > +RZ/G2L
> > +  and RZ/V2L SoCs.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - renesas,du-r9a07g044c # for RZ/G2LC compatible DU
> > +      - renesas,du-r9a07g044l # for RZ/G2L compatible DU
> 
> Please use the format "<manuf>,<soc>-<modulo>" for new bindings.
> 

OK.

> I thought there was no need to differentiate RZ/G2LC and RZ/G2L, as the
> only difference is a wiring difference due to the limited number of pins on
> the RZ/G2LC package, as per your confirmation[1]?
> Hence please just use "renesas,r9a07g044-du".

I cross checked HW manual, on the overview section(page 69) Supported
DU channels on various SoC's are as below

RZ/{G2L,V2L}
− 1 channel MIPI DSI interface or 1channel parallel output interface selectable,

RZ/G2LC
− 1 channel MIPI DSI interface

RZ/G2UL ( From RZ/G2UL hardware manual overview)
− 1 channel parallel output interface.

> 
> Do you want a family-specific compatible value ("rzg2l-"), as this IP block
> is shared by (at least) RZ/GL(C), RZ/V2L, and RZ/G2UL?

May be will conclude after the above discussion??

> 
> > +allOf:
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - renesas,du-r9a07g044c
> > +    then:
> > +      properties:
> > +        ports:
> > +          properties:
> > +            port@0:
> > +              description: DSI 0
> > +          required:
> > +            - port@0
> > +
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - renesas,du-r9a07g044l
> > +    then:
> > +      properties:
> > +        ports:
> > +          properties:
> > +            port@0:
> > +              description: DPAD 0
> > +            port@1:
> > +              description: DSI 0
> > +          required:
> > +            - port@0
> > +            - port@1
> 
> Having different port numbers for the common DSI0 output indeed complicates
> matters ;-)
> 

But we could delete as per [1] for RZ/G2LC where it supports only DSI and [2] for RZ/G2UL where it supports only DPI, right?

[1] https://github.com/renesas-rz/rz_linux-cip/blob/rz-5.10-cip1/arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi#L24

[2] https://github.com/renesas-rz/rz_linux-cip/blob/rz-5.10-cip1/arch/arm64/boot/dts/renesas/r9a07g043.dtsi#L1000

Regards,
Biju

Geert Uytterhoeven April 22, 2022, 8:34 a.m. UTC | #3

Hi Biju,

On Fri, Apr 22, 2022 at 10:11 AM Biju Das <[e-mail]> wrote:
> > Subject: Re: [PATCH v3 1/4] dt-bindings: display: Document Renesas RZ/G2L
> > DU bindings
> > On Thu, Apr 21, 2022 at 6:31 PM Biju Das <[e-mail]>
> > wrote:
> > > The RZ/G2L LCD controller is composed of Frame Compression Processor
> > > (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU).
> > >
> > > The DU module supports the following hardware features − Display
> > > Parallel Interface (DPI) and MIPI LINK Video Interface − Display
> > > timing master − Generates video timings − Selecting the polarity of
> > > output DCLK, HSYNC, VSYNC, and DE − Supports Progressive − Input data
> > > format (from VSPD): RGB888, RGB666 − Output data format: same as Input
> > > data format − Supporting Full HD (1920 pixels x 1080 lines) for
> > > MIPI-DSI Output − Supporting WXGA (1280 pixels x 800 lines) for
> > > Parallel Output
> > >
> > > This patch document DU module found on RZ/G2L LCDC.
> > >
> > > Signed-off-by: Biju Das <[e-mail]>
> >
> > Thanks for your patch!
> >
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
> > > @@ -0,0 +1,159 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > > +---
> > > +$id:
> > > +
> > > +title: Renesas RZ/G2L Display Unit (DU)
> > > +
> > > +maintainers:
> > > +  - Laurent Pinchart <[e-mail]>
> > > +  - Biju Das <[e-mail]>
> > > +
> > > +description: |
> > > +  These DT bindings describe the Display Unit embedded in the Renesas
> > > +RZ/G2L
> > > +  and RZ/V2L SoCs.
> > > +
> > > +properties:
> > > +  compatible:
> > > +    enum:
> > > +      - renesas,du-r9a07g044c # for RZ/G2LC compatible DU
> > > +      - renesas,du-r9a07g044l # for RZ/G2L compatible DU
> >
> > Please use the format "<manuf>,<soc>-<modulo>" for new bindings.
> >
>
> OK.
>
> > I thought there was no need to differentiate RZ/G2LC and RZ/G2L, as the
> > only difference is a wiring difference due to the limited number of pins on
> > the RZ/G2LC package, as per your confirmation[1]?
> > Hence please just use "renesas,r9a07g044-du".
>
> I cross checked HW manual, on the overview section(page 69) Supported
> DU channels on various SoC's are as below
>
> RZ/{G2L,V2L}
> − 1 channel MIPI DSI interface or 1channel parallel output interface selectable,
>
> RZ/G2LC
> − 1 channel MIPI DSI interface
>
> RZ/G2UL ( From RZ/G2UL hardware manual overview)
> − 1 channel parallel output interface.
>
> >
> > Do you want a family-specific compatible value ("rzg2l-"), as this IP block
> > is shared by (at least) RZ/GL(C), RZ/V2L, and RZ/G2UL?
>
> May be will conclude after the above discussion??

I don't insist on family-specific compatible values here, as the DUs on
RZ/G2UL and RZ/V2L may differ.
But RZ/G2L and RZ/G2LC are identical otherwise...

> > > +allOf:
> > > +  - if:
> > > +      properties:
> > > +        compatible:
> > > +          contains:
> > > +            enum:
> > > +              - renesas,du-r9a07g044c
> > > +    then:
> > > +      properties:
> > > +        ports:
> > > +          properties:
> > > +            port@0:
> > > +              description: DSI 0
> > > +          required:
> > > +            - port@0
> > > +
> > > +  - if:
> > > +      properties:
> > > +        compatible:
> > > +          contains:
> > > +            enum:
> > > +              - renesas,du-r9a07g044l
> > > +    then:
> > > +      properties:
> > > +        ports:
> > > +          properties:
> > > +            port@0:
> > > +              description: DPAD 0
> > > +            port@1:
> > > +              description: DSI 0
> > > +          required:
> > > +            - port@0
> > > +            - port@1
> >
> > Having different port numbers for the common DSI0 output indeed complicates
> > matters ;-)
>
> But we could delete as per [1] for RZ/G2LC where it supports only DSI and [2] for RZ/G2UL where it supports only DPI, right?
>
> [1] https://github.com/renesas-rz/rz_linux-cip/blob/rz-5.10-cip1/arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi#L24
>
> [2] https://github.com/renesas-rz/rz_linux-cip/blob/rz-5.10-cip1/arch/arm64/boot/dts/renesas/r9a07g043.dtsi#L1000

Yes we can. But as the internal hardware is the same, I think we
should keep the port numbers the same on RZ/G2L and RZ/G2LC.

For RZ/V2L, you probably want to treat it exactly the same as RZ/G2L,
i.e., the same port numbering.

For RZ/G2UL, you can use a different numbering, assuming no
family-specific compatible value is introduced.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [e-mail]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Biju Das April 22, 2022, 9:31 a.m. UTC | #4

Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH v3 1/4] dt-bindings: display: Document Renesas RZ/G2L
> DU bindings
> 
> Hi Biju,
> 
> On Fri, Apr 22, 2022 at 10:11 AM Biju Das <[e-mail]>
> wrote:
> > > Subject: Re: [PATCH v3 1/4] dt-bindings: display: Document Renesas
> > > RZ/G2L DU bindings On Thu, Apr 21, 2022 at 6:31 PM Biju Das
> > > <[e-mail]>
> > > wrote:
> > > > The RZ/G2L LCD controller is composed of Frame Compression
> > > > Processor (FCPVD), Video Signal Processor (VSPD), and Display Unit
> (DU).
> > > >
> > > > The DU module supports the following hardware features − Display
> > > > Parallel Interface (DPI) and MIPI LINK Video Interface − Display
> > > > timing master − Generates video timings − Selecting the polarity
> > > > of output DCLK, HSYNC, VSYNC, and DE − Supports Progressive −
> > > > Input data format (from VSPD): RGB888, RGB666 − Output data
> > > > format: same as Input data format − Supporting Full HD (1920
> > > > pixels x 1080 lines) for MIPI-DSI Output − Supporting WXGA (1280
> > > > pixels x 800 lines) for Parallel Output
> > > >
> > > > This patch document DU module found on RZ/G2L LCDC.
> > > >
> > > > Signed-off-by: Biju Das <[e-mail]>
> > >
> > > Thanks for your patch!
> > >
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.y
> > > > +++ aml
> > > > @@ -0,0 +1,159 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > > > +1.2
> > > > +---
> > > > +$id:
> > > > +
> > > > +title: Renesas RZ/G2L Display Unit (DU)
> > > > +
> > > > +maintainers:
> > > > +  - Laurent Pinchart <[e-mail]>
> > > > +  - Biju Das <[e-mail]>
> > > > +
> > > > +description: |
> > > > +  These DT bindings describe the Display Unit embedded in the
> > > > +Renesas RZ/G2L
> > > > +  and RZ/V2L SoCs.
> > > > +
> > > > +properties:
> > > > +  compatible:
> > > > +    enum:
> > > > +      - renesas,du-r9a07g044c # for RZ/G2LC compatible DU
> > > > +      - renesas,du-r9a07g044l # for RZ/G2L compatible DU
> > >
> > > Please use the format "<manuf>,<soc>-<modulo>" for new bindings.
> > >
> >
> > OK.
> >
> > > I thought there was no need to differentiate RZ/G2LC and RZ/G2L, as
> > > the only difference is a wiring difference due to the limited number
> > > of pins on the RZ/G2LC package, as per your confirmation[1]?
> > > Hence please just use "renesas,r9a07g044-du".
> >
> > I cross checked HW manual, on the overview section(page 69) Supported
> > DU channels on various SoC's are as below
> >
> > RZ/{G2L,V2L}
> > − 1 channel MIPI DSI interface or 1channel parallel output interface
> > selectable,
> >
> > RZ/G2LC
> > − 1 channel MIPI DSI interface
> >
> > RZ/G2UL ( From RZ/G2UL hardware manual overview) − 1 channel parallel
> > output interface.
> >
> > >
> > > Do you want a family-specific compatible value ("rzg2l-"), as this
> > > IP block is shared by (at least) RZ/GL(C), RZ/V2L, and RZ/G2UL?
> >
> > May be will conclude after the above discussion??
> 
> I don't insist on family-specific compatible values here, as the DUs on
> RZ/G2UL and RZ/V2L may differ.
> But RZ/G2L and RZ/G2LC are identical otherwise...

OK, Will use

compatible:
    items:
     - enum:
         - renesas,r9a07g044-du # RZ/G2{L,LC}
     - const: renesas,rzg2l-du

> 
> > > > +allOf:
> > > > +  - if:
> > > > +      properties:
> > > > +        compatible:
> > > > +          contains:
> > > > +            enum:
> > > > +              - renesas,du-r9a07g044c
> > > > +    then:
> > > > +      properties:
> > > > +        ports:
> > > > +          properties:
> > > > +            port@0:
> > > > +              description: DSI 0
> > > > +          required:
> > > > +            - port@0
> > > > +
> > > > +  - if:
> > > > +      properties:
> > > > +        compatible:
> > > > +          contains:
> > > > +            enum:
> > > > +              - renesas,du-r9a07g044l
> > > > +    then:
> > > > +      properties:
> > > > +        ports:
> > > > +          properties:
> > > > +            port@0:
> > > > +              description: DPAD 0
> > > > +            port@1:
> > > > +              description: DSI 0
> > > > +          required:
> > > > +            - port@0
> > > > +            - port@1
> > >
> > > Having different port numbers for the common DSI0 output indeed
> > > complicates matters ;-)
> >
> > But we could delete as per [1] for RZ/G2LC where it supports only DSI and
> [2] for RZ/G2UL where it supports only DPI, right?
> 
> Yes we can. But as the internal hardware is the same, I think we should
> keep the port numbers the same on RZ/G2L and RZ/G2LC.

OK, Will keep the same port number for both RZ/G2L and RZ/G2LC.

> 
> For RZ/V2L, you probably want to treat it exactly the same as RZ/G2L, i.e.,
> the same port numbering.

OK.

> 
> For RZ/G2UL, you can use a different numbering, assuming no family-specific
> compatible value is introduced.

OK.

Regards,
Biju

Geert Uytterhoeven April 22, 2022, 3:12 p.m. UTC | #5

Hi Biju,

On Fri, Apr 22, 2022 at 11:31 AM Biju Das <[e-mail]> wrote:
> > Subject: Re: [PATCH v3 1/4] dt-bindings: display: Document Renesas RZ/G2L
> > DU bindings
> > On Fri, Apr 22, 2022 at 10:11 AM Biju Das <[e-mail]>
> > wrote:
> > > > Subject: Re: [PATCH v3 1/4] dt-bindings: display: Document Renesas
> > > > RZ/G2L DU bindings On Thu, Apr 21, 2022 at 6:31 PM Biju Das
> > > > <[e-mail]>
> > > > wrote:
> > > > > The RZ/G2L LCD controller is composed of Frame Compression
> > > > > Processor (FCPVD), Video Signal Processor (VSPD), and Display Unit
> > (DU).
> > > > >
> > > > > The DU module supports the following hardware features − Display
> > > > > Parallel Interface (DPI) and MIPI LINK Video Interface − Display
> > > > > timing master − Generates video timings − Selecting the polarity
> > > > > of output DCLK, HSYNC, VSYNC, and DE − Supports Progressive −
> > > > > Input data format (from VSPD): RGB888, RGB666 − Output data
> > > > > format: same as Input data format − Supporting Full HD (1920
> > > > > pixels x 1080 lines) for MIPI-DSI Output − Supporting WXGA (1280
> > > > > pixels x 800 lines) for Parallel Output
> > > > >
> > > > > This patch document DU module found on RZ/G2L LCDC.
> > > > >
> > > > > Signed-off-by: Biju Das <[e-mail]>
> > > >
> > > > Thanks for your patch!
> > > >
> > > > > --- /dev/null
> > > > > +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.y
> > > > > +++ aml
> > > > > @@ -0,0 +1,159 @@
> > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > > > > +1.2
> > > > > +---
> > > > > +$id:
> > > > > +
> > > > > +title: Renesas RZ/G2L Display Unit (DU)
> > > > > +
> > > > > +maintainers:
> > > > > +  - Laurent Pinchart <[e-mail]>
> > > > > +  - Biju Das <[e-mail]>
> > > > > +
> > > > > +description: |
> > > > > +  These DT bindings describe the Display Unit embedded in the
> > > > > +Renesas RZ/G2L
> > > > > +  and RZ/V2L SoCs.
> > > > > +
> > > > > +properties:
> > > > > +  compatible:
> > > > > +    enum:
> > > > > +      - renesas,du-r9a07g044c # for RZ/G2LC compatible DU
> > > > > +      - renesas,du-r9a07g044l # for RZ/G2L compatible DU
> > > >
> > > > Please use the format "<manuf>,<soc>-<modulo>" for new bindings.
> > > >
> > >
> > > OK.
> > >
> > > > I thought there was no need to differentiate RZ/G2LC and RZ/G2L, as
> > > > the only difference is a wiring difference due to the limited number
> > > > of pins on the RZ/G2LC package, as per your confirmation[1]?
> > > > Hence please just use "renesas,r9a07g044-du".
> > >
> > > I cross checked HW manual, on the overview section(page 69) Supported
> > > DU channels on various SoC's are as below
> > >
> > > RZ/{G2L,V2L}
> > > − 1 channel MIPI DSI interface or 1channel parallel output interface
> > > selectable,
> > >
> > > RZ/G2LC
> > > − 1 channel MIPI DSI interface
> > >
> > > RZ/G2UL ( From RZ/G2UL hardware manual overview) − 1 channel parallel
> > > output interface.
> > >
> > > >
> > > > Do you want a family-specific compatible value ("rzg2l-"), as this
> > > > IP block is shared by (at least) RZ/GL(C), RZ/V2L, and RZ/G2UL?
> > >
> > > May be will conclude after the above discussion??
> >
> > I don't insist on family-specific compatible values here, as the DUs on
> > RZ/G2UL and RZ/V2L may differ.
> > But RZ/G2L and RZ/G2LC are identical otherwise...
>
> OK, Will use
>
> compatible:
>     items:
>      - enum:
>          - renesas,r9a07g044-du # RZ/G2{L,LC}
>      - const: renesas,rzg2l-du

Please drop "renesas,rzg2l-du"...

> >
> > > > > +allOf:
> > > > > +  - if:
> > > > > +      properties:
> > > > > +        compatible:
> > > > > +          contains:
> > > > > +            enum:
> > > > > +              - renesas,du-r9a07g044c
> > > > > +    then:
> > > > > +      properties:
> > > > > +        ports:
> > > > > +          properties:
> > > > > +            port@0:
> > > > > +              description: DSI 0
> > > > > +          required:
> > > > > +            - port@0
> > > > > +
> > > > > +  - if:
> > > > > +      properties:
> > > > > +        compatible:
> > > > > +          contains:
> > > > > +            enum:
> > > > > +              - renesas,du-r9a07g044l
> > > > > +    then:
> > > > > +      properties:
> > > > > +        ports:
> > > > > +          properties:
> > > > > +            port@0:
> > > > > +              description: DPAD 0
> > > > > +            port@1:
> > > > > +              description: DSI 0
> > > > > +          required:
> > > > > +            - port@0
> > > > > +            - port@1
> > > >
> > > > Having different port numbers for the common DSI0 output indeed
> > > > complicates matters ;-)
> > >
> > > But we could delete as per [1] for RZ/G2LC where it supports only DSI and
> > [2] for RZ/G2UL where it supports only DPI, right?
> >
> > Yes we can. But as the internal hardware is the same, I think we should
> > keep the port numbers the same on RZ/G2L and RZ/G2LC.
>
> OK, Will keep the same port number for both RZ/G2L and RZ/G2LC.
>
> >
> > For RZ/V2L, you probably want to treat it exactly the same as RZ/G2L, i.e.,
> > the same port numbering.
>
> OK.
>
> >
> > For RZ/G2UL, you can use a different numbering, assuming no family-specific
> > compatible value is introduced.
>
> OK.

... as that will interfere here.  If the numbering will be SoC-specific,
the driver has to match on the SoC-specific compatible value anyway.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [e-mail]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Patch

diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
new file mode 100644
index 000000000000..2ee2d713cef4
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
@@ -0,0 +1,159 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/renesas,rzg2l-du.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L Display Unit (DU)
+
+maintainers:
+  - Laurent Pinchart <[e-mail]>
+  - Biju Das <[e-mail]>
+
+description: |
+  These DT bindings describe the Display Unit embedded in the Renesas RZ/G2L
+  and RZ/V2L SoCs.
+
+properties:
+  compatible:
+    enum:
+      - renesas,du-r9a07g044c # for RZ/G2LC compatible DU
+      - renesas,du-r9a07g044l # for RZ/G2L compatible DU
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Main clock
+      - description: Register access clock
+      - description: Video clock
+
+  clock-names:
+    items:
+      - const: aclk
+      - const: pclk
+      - const: vclk
+
+  resets:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    description: |
+      The connections to the DU output video ports are modeled using the OF
+      graph bindings specified in Documentation/devicetree/bindings/graph.txt.
+      The number of ports and their assignment are model-dependent. Each port
+      shall have a single endpoint.
+
+    patternProperties:
+      "^port@[0-1]$":
+        $ref: /schemas/graph.yaml#/properties/port
+        unevaluatedProperties: false
+
+    required:
+      - port@0
+
+    unevaluatedProperties: false
+
+  renesas,vsps:
+    $ref: "/schemas/types.yaml#/definitions/phandle-array"
+    items:
+      items:
+        - description: phandle to VSP instance that serves the DU channel
+        - description: Channel index identifying the LIF instance in that VSP
+    description:
+      A list of phandle and channel index tuples to the VSPs that handle the
+      memory interfaces for the DU channels.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - power-domains
+  - ports
+  - renesas,vsps
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,du-r9a07g044c
+    then:
+      properties:
+        ports:
+          properties:
+            port@0:
+              description: DSI 0
+          required:
+            - port@0
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,du-r9a07g044l
+    then:
+      properties:
+        ports:
+          properties:
+            port@0:
+              description: DPAD 0
+            port@1:
+              description: DSI 0
+          required:
+            - port@0
+            - port@1
+
+additionalProperties: false
+
+examples:
+  # RZ/G2L DU
+  - |
+    #include <dt-bindings/clock/r9a07g044-cpg.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    display@10890000 {
+        compatible = "renesas,du-r9a07g044l";
+        reg = <0x10890000 0x10000>;
+        interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
+                 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
+                 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
+        clock-names = "aclk", "pclk", "vclk";
+        resets = <&cpg R9A07G044_LCDC_RESET_N>;
+        power-domains = <&cpg>;
+
+        renesas,vsps = <&vspd0 0>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+                du_out_rgb: endpoint {
+                };
+            };
+            port@1 {
+                reg = <1>;
+                du_out_dsi0: endpoint {
+                    remote-endpoint = <&dsi0_in>;
+                };
+            };
+        };
+    };
+
+...