| Message ID | 1647919631-14447-2-git-send-email-quic_vpolimer@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | Update mdp clk to max supported value to support higher refresh rates | expand |
Hi, On Mon, Mar 21, 2022 at 8:27 PM Vinod Polimera <quic_vpolimer@quicinc.com> wrote: > > Set mdp clock to max clock rate during probe/bind sequence from the > opp table so that rails are not at undetermined state. Since we do not > know what will be the rate set in boot loader, it would be ideal to > vote at max frequency. There could be a firmware display programmed > in bootloader and we want to transition it to kernel without underflowing. > The clock will be scaled down later when framework sends an update. > > Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") > Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > Reviewed-by: Douglas Anderson <dianders@chromium.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8 ++++++++ > 1 file changed, 8 insertions(+) Just wanted to confirm that this patch will be queued up somewhat soon. I think it's good to go but I don't see it in any trees yet. ;-) FWIW, I can also say that I've tested this patch and it fixes the underrun issues on sc7280-herobrine-rev1. Tested-by: Douglas Anderson <dianders@chromium.org> -Doug
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index e29796c..9c346ce 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1202,7 +1202,9 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) struct platform_device *pdev = to_platform_device(dev); struct drm_device *ddev = priv->dev; struct dpu_kms *dpu_kms; + struct dev_pm_opp *opp; int ret = 0; + unsigned long max_freq = ULONG_MAX; dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL); if (!dpu_kms) @@ -1225,6 +1227,12 @@ static int dpu_bind(struct device *dev, struct device *master, void *data) } dpu_kms->num_clocks = ret; + opp = dev_pm_opp_find_freq_floor(dev, &max_freq); + if (!IS_ERR(opp)) + dev_pm_opp_put(opp); + + dev_pm_opp_set_rate(dev, max_freq); + platform_set_drvdata(pdev, dpu_kms); ret = msm_kms_init(&dpu_kms->base, &kms_funcs);
Set mdp clock to max clock rate during probe/bind sequence from the opp table so that rails are not at undetermined state. Since we do not know what will be the rate set in boot loader, it would be ideal to vote at max frequency. There could be a firmware display programmed in bootloader and we want to transition it to kernel without underflowing. The clock will be scaled down later when framework sends an update. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8 ++++++++ 1 file changed, 8 insertions(+)