| Message ID | 20220425105346.324864-1-benjamin.gaignard@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | media: hantro: HEVC: unconditionnaly set pps_{cb/cr}_qp_offset values | expand |
On Mon, Apr 25, 2022 at 7:53 AM Benjamin Gaignard <benjamin.gaignard@collabora.com> wrote: > > Always set pps_cb_qp_offset and pps_cr_qp_offset values in Hantro/G2 > register whatever is V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT > flag value. > This fix a couple of tests in fluster. > Which tests? Thanks, Ezequiel > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> > --- > drivers/staging/media/hantro/hantro_g2_hevc_dec.c | 9 ++------- > 1 file changed, 2 insertions(+), 7 deletions(-) > > diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c > index 2c8eb0720db8..bb512389c1a5 100644 > --- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c > +++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c > @@ -194,13 +194,8 @@ static void set_params(struct hantro_ctx *ctx) > hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0); > } > > - if (pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT) { > - hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset); > - hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset); > - } else { > - hantro_reg_write(vpu, &g2_cb_qp_offset, 0); > - hantro_reg_write(vpu, &g2_cr_qp_offset, 0); > - } > + hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset); > + hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset); > > hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2); > hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2); > -- > 2.32.0 >
Le 25/04/2022 à 14:12, Ezequiel Garcia a écrit : > On Mon, Apr 25, 2022 at 7:53 AM Benjamin Gaignard > <benjamin.gaignard@collabora.com> wrote: >> Always set pps_cb_qp_offset and pps_cr_qp_offset values in Hantro/G2 >> register whatever is V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT >> flag value. >> This fix a couple of tests in fluster. >> > Which tests? CAINIT_G_SHARP_3 test. Hantro proprietary stack (g2dec tool) does the same. Regards, Benjamin > > Thanks, > Ezequiel > >> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> >> --- >> drivers/staging/media/hantro/hantro_g2_hevc_dec.c | 9 ++------- >> 1 file changed, 2 insertions(+), 7 deletions(-) >> >> diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c >> index 2c8eb0720db8..bb512389c1a5 100644 >> --- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c >> +++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c >> @@ -194,13 +194,8 @@ static void set_params(struct hantro_ctx *ctx) >> hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0); >> } >> >> - if (pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT) { >> - hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset); >> - hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset); >> - } else { >> - hantro_reg_write(vpu, &g2_cb_qp_offset, 0); >> - hantro_reg_write(vpu, &g2_cr_qp_offset, 0); >> - } >> + hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset); >> + hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset); >> >> hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2); >> hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2); >> -- >> 2.32.0 >>
On Mon, Apr 25, 2022 at 12:28 PM Benjamin Gaignard <benjamin.gaignard@collabora.com> wrote: > > > Le 25/04/2022 à 14:12, Ezequiel Garcia a écrit : > > On Mon, Apr 25, 2022 at 7:53 AM Benjamin Gaignard > > <benjamin.gaignard@collabora.com> wrote: > >> Always set pps_cb_qp_offset and pps_cr_qp_offset values in Hantro/G2 > >> register whatever is V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT > >> flag value. > >> This fix a couple of tests in fluster. > >> > > Which tests? > > CAINIT_G_SHARP_3 test. > Hantro proprietary stack (g2dec tool) does the same. > Can you resend adding this information to the commit description? Thanks, Ezequiel > Regards, > Benjamin > > > > > Thanks, > > Ezequiel > > > >> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> > >> --- > >> drivers/staging/media/hantro/hantro_g2_hevc_dec.c | 9 ++------- > >> 1 file changed, 2 insertions(+), 7 deletions(-) > >> > >> diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c > >> index 2c8eb0720db8..bb512389c1a5 100644 > >> --- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c > >> +++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c > >> @@ -194,13 +194,8 @@ static void set_params(struct hantro_ctx *ctx) > >> hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0); > >> } > >> > >> - if (pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT) { > >> - hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset); > >> - hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset); > >> - } else { > >> - hantro_reg_write(vpu, &g2_cb_qp_offset, 0); > >> - hantro_reg_write(vpu, &g2_cr_qp_offset, 0); > >> - } > >> + hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset); > >> + hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset); > >> > >> hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2); > >> hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2); > >> -- > >> 2.32.0 > >>
diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c index 2c8eb0720db8..bb512389c1a5 100644 --- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c +++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c @@ -194,13 +194,8 @@ static void set_params(struct hantro_ctx *ctx) hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0); } - if (pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT) { - hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset); - hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset); - } else { - hantro_reg_write(vpu, &g2_cb_qp_offset, 0); - hantro_reg_write(vpu, &g2_cr_qp_offset, 0); - } + hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset); + hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset); hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2); hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2);
Always set pps_cb_qp_offset and pps_cr_qp_offset values in Hantro/G2 register whatever is V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT flag value. This fix a couple of tests in fluster. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> --- drivers/staging/media/hantro/hantro_g2_hevc_dec.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-)