| Message ID | 20220413073618.291335-1-vishal.l.verma@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | PCI/ACPI: add support for CXL _OSC | expand |
On Wed, 2022-04-13 at 01:36 -0600, Vishal Verma wrote: > Changes since v5[1]: > - Collect an reviewed-by tags from Rafael, Adam, and David > - Fix a couple of missed s/CXL/extended/ in acpi_bus.h (Rafael) Rafael, or Bjorn, Dan has offered to take this through cxl.git. Any objections to that - would you prefer it to go through either the PCI or ACPI trees instead? > > Add support for using the CXL definition of _OSC where applicable, and > negotiating CXL specific support and control bits. > > Patch 1 is a preliminary cleanup that replaces open-coded pointer > arithmetic to retrieve the Control DWORD with an inline helper. > > Patch 2 adds the new CXL _OSC UUID, and uses it instead of the PCI UUID > when a root port is CXL enabled. It provides a fallback method for > CXL-1.1 platforms that may not implement the CXL-2.0 _OSC. > > Patch 3 performs negotiation for the CXL specific _OSC support and > control bits. > > I've tested these against a custom qemu[2], which adds the CXL _OSC (in > addition to other CXL support). Specifically, _OSC support is added > here[3]. > > [1]: https://lore.kernel.org/linux-cxl/20220406023746.2807328-1-vishal.l.verma@intel.com > [2]: https://gitlab.com/jic23/qemu/-/tree/cxl-v8-draft > [3]: https://gitlab.com/jic23/qemu/-/commit/1d67df6b6e3716c27462873f3451956f5c0673a3 > > Dan Williams (1): > PCI/ACPI: Prefer CXL _OSC instead of PCIe _OSC for CXL host bridges > > Vishal Verma (2): > PCI/ACPI: add a helper for retrieving _OSC Control DWORDs > PCI/ACPI: negotiate CXL _OSC > > include/linux/acpi.h | 42 ++++++- > include/acpi/acpi_bus.h | 12 +- > drivers/acpi/bus.c | 2 +- > drivers/acpi/pci_root.c | 240 +++++++++++++++++++++++++++++++++++----- > 4 files changed, 262 insertions(+), 34 deletions(-) > > > base-commit: 05e815539f3f161585c13a9ab023341bade2c52f
On 4/23/2022 12:24 AM, Verma, Vishal L wrote: > On Wed, 2022-04-13 at 01:36 -0600, Vishal Verma wrote: >> Changes since v5[1]: >> - Collect an reviewed-by tags from Rafael, Adam, and David >> - Fix a couple of missed s/CXL/extended/ in acpi_bus.h (Rafael) > Rafael, or Bjorn, > > Dan has offered to take this through cxl.git. Any objections to that - > would you prefer it to go through either the PCI or ACPI trees instead? This would be fine with me, but I can take the series too. >> Add support for using the CXL definition of _OSC where applicable, and >> negotiating CXL specific support and control bits. >> >> Patch 1 is a preliminary cleanup that replaces open-coded pointer >> arithmetic to retrieve the Control DWORD with an inline helper. >> >> Patch 2 adds the new CXL _OSC UUID, and uses it instead of the PCI UUID >> when a root port is CXL enabled. It provides a fallback method for >> CXL-1.1 platforms that may not implement the CXL-2.0 _OSC. >> >> Patch 3 performs negotiation for the CXL specific _OSC support and >> control bits. >> >> I've tested these against a custom qemu[2], which adds the CXL _OSC (in >> addition to other CXL support). Specifically, _OSC support is added >> here[3]. >> >> [1]: https://lore.kernel.org/linux-cxl/20220406023746.2807328-1-vishal.l.verma@intel.com >> [2]: https://gitlab.com/jic23/qemu/-/tree/cxl-v8-draft >> [3]: https://gitlab.com/jic23/qemu/-/commit/1d67df6b6e3716c27462873f3451956f5c0673a3 >> >> Dan Williams (1): >> PCI/ACPI: Prefer CXL _OSC instead of PCIe _OSC for CXL host bridges >> >> Vishal Verma (2): >> PCI/ACPI: add a helper for retrieving _OSC Control DWORDs >> PCI/ACPI: negotiate CXL _OSC >> >> include/linux/acpi.h | 42 ++++++- >> include/acpi/acpi_bus.h | 12 +- >> drivers/acpi/bus.c | 2 +- >> drivers/acpi/pci_root.c | 240 +++++++++++++++++++++++++++++++++++----- >> 4 files changed, 262 insertions(+), 34 deletions(-) >> >> >> base-commit: 05e815539f3f161585c13a9ab023341bade2c52f
On Fri, Apr 22, 2022 at 10:24:34PM +0000, Verma, Vishal L wrote: > On Wed, 2022-04-13 at 01:36 -0600, Vishal Verma wrote: > > Changes since v5[1]: > > - Collect an reviewed-by tags from Rafael, Adam, and David > > - Fix a couple of missed s/CXL/extended/ in acpi_bus.h (Rafael) > > Rafael, or Bjorn, > > Dan has offered to take this through cxl.git. Any objections to that - > would you prefer it to go through either the PCI or ACPI trees instead? OK by me if Dan or Rafael takes it.
On Mon, Apr 25, 2022 at 11:14 AM Bjorn Helgaas <helgaas@kernel.org> wrote: > > On Fri, Apr 22, 2022 at 10:24:34PM +0000, Verma, Vishal L wrote: > > On Wed, 2022-04-13 at 01:36 -0600, Vishal Verma wrote: > > > Changes since v5[1]: > > > - Collect an reviewed-by tags from Rafael, Adam, and David > > > - Fix a couple of missed s/CXL/extended/ in acpi_bus.h (Rafael) > > > > Rafael, or Bjorn, > > > > Dan has offered to take this through cxl.git. Any objections to that - > > would you prefer it to go through either the PCI or ACPI trees instead? > > OK by me if Dan or Rafael takes it. Thanks Bjorn, and Rafael. It simplifies a few things if it is kept with the other CXL changes for this merge cycle, so I'll take it through cxl.git.
On 4/25/2022 8:13 PM, Bjorn Helgaas wrote: > On Fri, Apr 22, 2022 at 10:24:34PM +0000, Verma, Vishal L wrote: >> On Wed, 2022-04-13 at 01:36 -0600, Vishal Verma wrote: >>> Changes since v5[1]: >>> - Collect an reviewed-by tags from Rafael, Adam, and David >>> - Fix a couple of missed s/CXL/extended/ in acpi_bus.h (Rafael) >> Rafael, or Bjorn, >> >> Dan has offered to take this through cxl.git. Any objections to that - >> would you prefer it to go through either the PCI or ACPI trees instead? > OK by me if Dan or Rafael takes it. All right, so it depends on whether or not there's any pending material for the CXL tree that will depend on these patches. If so, it likely is better to route them via CXL.