| Message ID | 20220427162131.3127303-1-l.stach@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: imx8mp: add clkout1/2 support | expand |
On 22-04-27 18:21:31, Lucas Stach wrote: > clkout1 and clkout2 allow to supply clocks from the SoC to the board, > which is used by some board designs to provide reference clocks. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> > --- > drivers/clk/imx/clk-imx8mp.c | 14 ++++++++++++++ > include/dt-bindings/clock/imx8mp-clock.h | 9 ++++++++- > 2 files changed, 22 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c > index 18f5b7c3ca9d..48099a2ed6b2 100644 > --- a/drivers/clk/imx/clk-imx8mp.c > +++ b/drivers/clk/imx/clk-imx8mp.c > @@ -399,6 +399,11 @@ static const char * const imx8mp_sai7_sels[] = {"osc_24m", "audio_pll1_out", "au > > static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; > > +static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out", > + "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", > + "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", > + "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; > + > static struct clk_hw **hws; > static struct clk_hw_onecell_data *clk_hw_data; > > @@ -504,6 +509,15 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) > hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); > hws[IMX8MP_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); > > + hws[IMX8MP_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", anatop_base + 0x128, 4, 4, > + imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels)); > + hws[IMX8MP_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", anatop_base + 0x128, 0, 4); > + hws[IMX8MP_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", anatop_base + 0x128, 8); > + hws[IMX8MP_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", anatop_base + 0x128, 20, 4, > + imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels)); > + hws[IMX8MP_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", anatop_base + 0x128, 16, 4); > + hws[IMX8MP_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", anatop_base + 0x128, 24); > + > hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000); > hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV]; > hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV]; > diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h > index 235c7a00d379..7a6b45a04c24 100644 > --- a/include/dt-bindings/clock/imx8mp-clock.h > +++ b/include/dt-bindings/clock/imx8mp-clock.h > @@ -318,7 +318,14 @@ > #define IMX8MP_CLK_HSIO_AXI 311 > #define IMX8MP_CLK_MEDIA_ISP 312 > > -#define IMX8MP_CLK_END 313 > +#define IMX8MP_CLK_CLKOUT1_SEL 313 > +#define IMX8MP_CLK_CLKOUT1_DIV 314 > +#define IMX8MP_CLK_CLKOUT1 315 > +#define IMX8MP_CLK_CLKOUT2_SEL 316 > +#define IMX8MP_CLK_CLKOUT2_DIV 317 > +#define IMX8MP_CLK_CLKOUT2 318 > + > +#define IMX8MP_CLK_END 319 > > #define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 > #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 > -- > 2.30.2 >
On 22-04-27 18:21:31, Lucas Stach wrote: > clkout1 and clkout2 allow to supply clocks from the SoC to the board, > which is used by some board designs to provide reference clocks. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Applied, thanks! > --- > drivers/clk/imx/clk-imx8mp.c | 14 ++++++++++++++ > include/dt-bindings/clock/imx8mp-clock.h | 9 ++++++++- > 2 files changed, 22 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c > index 18f5b7c3ca9d..48099a2ed6b2 100644 > --- a/drivers/clk/imx/clk-imx8mp.c > +++ b/drivers/clk/imx/clk-imx8mp.c > @@ -399,6 +399,11 @@ static const char * const imx8mp_sai7_sels[] = {"osc_24m", "audio_pll1_out", "au > > static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; > > +static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out", > + "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", > + "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", > + "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; > + > static struct clk_hw **hws; > static struct clk_hw_onecell_data *clk_hw_data; > > @@ -504,6 +509,15 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) > hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); > hws[IMX8MP_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); > > + hws[IMX8MP_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", anatop_base + 0x128, 4, 4, > + imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels)); > + hws[IMX8MP_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", anatop_base + 0x128, 0, 4); > + hws[IMX8MP_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", anatop_base + 0x128, 8); > + hws[IMX8MP_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", anatop_base + 0x128, 20, 4, > + imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels)); > + hws[IMX8MP_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", anatop_base + 0x128, 16, 4); > + hws[IMX8MP_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", anatop_base + 0x128, 24); > + > hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000); > hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV]; > hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV]; > diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h > index 235c7a00d379..7a6b45a04c24 100644 > --- a/include/dt-bindings/clock/imx8mp-clock.h > +++ b/include/dt-bindings/clock/imx8mp-clock.h > @@ -318,7 +318,14 @@ > #define IMX8MP_CLK_HSIO_AXI 311 > #define IMX8MP_CLK_MEDIA_ISP 312 > > -#define IMX8MP_CLK_END 313 > +#define IMX8MP_CLK_CLKOUT1_SEL 313 > +#define IMX8MP_CLK_CLKOUT1_DIV 314 > +#define IMX8MP_CLK_CLKOUT1 315 > +#define IMX8MP_CLK_CLKOUT2_SEL 316 > +#define IMX8MP_CLK_CLKOUT2_DIV 317 > +#define IMX8MP_CLK_CLKOUT2 318 > + > +#define IMX8MP_CLK_END 319 > > #define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 > #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 > -- > 2.30.2 >
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index 18f5b7c3ca9d..48099a2ed6b2 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -399,6 +399,11 @@ static const char * const imx8mp_sai7_sels[] = {"osc_24m", "audio_pll1_out", "au static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; +static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out", + "dummy", "dummy", "gpu_pll_out", "vpu_pll_out", + "arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3", + "dummy", "dummy", "osc_24m", "dummy", "osc_32k"}; + static struct clk_hw **hws; static struct clk_hw_onecell_data *clk_hw_data; @@ -504,6 +509,15 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); hws[IMX8MP_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); + hws[IMX8MP_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", anatop_base + 0x128, 4, 4, + imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels)); + hws[IMX8MP_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", anatop_base + 0x128, 0, 4); + hws[IMX8MP_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", anatop_base + 0x128, 8); + hws[IMX8MP_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", anatop_base + 0x128, 20, 4, + imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels)); + hws[IMX8MP_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", anatop_base + 0x128, 16, 4); + hws[IMX8MP_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", anatop_base + 0x128, 24); + hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000); hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV]; hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV]; diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index 235c7a00d379..7a6b45a04c24 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -318,7 +318,14 @@ #define IMX8MP_CLK_HSIO_AXI 311 #define IMX8MP_CLK_MEDIA_ISP 312 -#define IMX8MP_CLK_END 313 +#define IMX8MP_CLK_CLKOUT1_SEL 313 +#define IMX8MP_CLK_CLKOUT1_DIV 314 +#define IMX8MP_CLK_CLKOUT1 315 +#define IMX8MP_CLK_CLKOUT2_SEL 316 +#define IMX8MP_CLK_CLKOUT2_DIV 317 +#define IMX8MP_CLK_CLKOUT2 318 + +#define IMX8MP_CLK_END 319 #define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 #define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1
clkout1 and clkout2 allow to supply clocks from the SoC to the board, which is used by some board designs to provide reference clocks. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- drivers/clk/imx/clk-imx8mp.c | 14 ++++++++++++++ include/dt-bindings/clock/imx8mp-clock.h | 9 ++++++++- 2 files changed, 22 insertions(+), 1 deletion(-)