| Message ID | 20220502163417.2635462-1-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | i915: Introduce Ponte Vecchio | expand |
On 02/05/2022 17:34, Matt Roper wrote: > Ponte Vecchio (PVC) is a new GPU based on the Xe_HPC architecture. As a > compute-focused platform, PVC has compute engines and enhanced copy > engines, but no render engine (there is no geometry pipeline) and no > display. > > This is just a handful of early enablement patches, including some > initial support for the new copy engines (although we're not yet adding > those to the platform's engine list or exposing them to userspace just > yet). IMO lets hold off merging this until next week if that sounds acceptable? This week I need to do a final pull for final bits of DG2 and I would like to keep it as small as possible. Regards, Tvrtko > > Ayaz A Siddiqui (1): > drm/i915/pvc: Define MOCS table for PVC > > John Harrison (1): > drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter > engine > > Lucas De Marchi (2): > drm/i915/pvc: skip all copy engines from aux table invalidate > drm/i915/pvc: read fuses for link copy engines > > Matt Roper (5): > drm/i915/pvc: Add forcewake support > drm/i915/pvc: Read correct RP_STATE_CAP register > drm/i915/pvc: Engines definitions for new copy engines > drm/i915/pvc: Interrupt support for new copy engines > drm/i915/pvc: Reset support for new copy engines > > Stuart Summers (2): > drm/i915/pvc: add initial Ponte Vecchio definitions > drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL > > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 20 ++- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 92 +++++++++++ > drivers/gpu/drm/i915/gt/intel_engine_types.h | 10 +- > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 12 +- > drivers/gpu/drm/i915/gt/intel_gt_irq.c | 16 ++ > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 56 ++++--- > drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 + > drivers/gpu/drm/i915/gt/intel_mocs.c | 24 ++- > drivers/gpu/drm/i915/gt/intel_rps.c | 4 +- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 13 +- > drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 9 +- > drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +- > drivers/gpu/drm/i915/i915_drv.h | 6 + > drivers/gpu/drm/i915/i915_pci.c | 23 +++ > drivers/gpu/drm/i915/i915_reg.h | 9 ++ > drivers/gpu/drm/i915/intel_device_info.c | 1 + > drivers/gpu/drm/i915/intel_device_info.h | 5 +- > drivers/gpu/drm/i915/intel_uncore.c | 150 +++++++++++++++++- > drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 + > 19 files changed, 417 insertions(+), 38 deletions(-) >
On Tue, May 03, 2022 at 09:21:04AM +0100, Tvrtko Ursulin wrote: > > On 02/05/2022 17:34, Matt Roper wrote: > > Ponte Vecchio (PVC) is a new GPU based on the Xe_HPC architecture. As a > > compute-focused platform, PVC has compute engines and enhanced copy > > engines, but no render engine (there is no geometry pipeline) and no > > display. > > > > This is just a handful of early enablement patches, including some > > initial support for the new copy engines (although we're not yet adding > > those to the platform's engine list or exposing them to userspace just > > yet). > > IMO lets hold off merging this until next week if that sounds acceptable? > This week I need to do a final pull for final bits of DG2 and I would like > to keep it as small as possible. I was wondering if we should try to apply patch #1 quickly, just to get the IS_PONTEVECCHIO definition into the tree early and minimize the cross-tree merge hassles down the road? Although I guess PVC might not be as big a problem as some platforms since no display means that we won't have a huge split of patches between -next and -gt-next that both need the basic defines present. Matt > > Regards, > > Tvrtko > > > > > Ayaz A Siddiqui (1): > > drm/i915/pvc: Define MOCS table for PVC > > > > John Harrison (1): > > drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter > > engine > > > > Lucas De Marchi (2): > > drm/i915/pvc: skip all copy engines from aux table invalidate > > drm/i915/pvc: read fuses for link copy engines > > > > Matt Roper (5): > > drm/i915/pvc: Add forcewake support > > drm/i915/pvc: Read correct RP_STATE_CAP register > > drm/i915/pvc: Engines definitions for new copy engines > > drm/i915/pvc: Interrupt support for new copy engines > > drm/i915/pvc: Reset support for new copy engines > > > > Stuart Summers (2): > > drm/i915/pvc: add initial Ponte Vecchio definitions > > drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL > > > > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 20 ++- > > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 92 +++++++++++ > > drivers/gpu/drm/i915/gt/intel_engine_types.h | 10 +- > > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 12 +- > > drivers/gpu/drm/i915/gt/intel_gt_irq.c | 16 ++ > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 56 ++++--- > > drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 + > > drivers/gpu/drm/i915/gt/intel_mocs.c | 24 ++- > > drivers/gpu/drm/i915/gt/intel_rps.c | 4 +- > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 13 +- > > drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 9 +- > > drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +- > > drivers/gpu/drm/i915/i915_drv.h | 6 + > > drivers/gpu/drm/i915/i915_pci.c | 23 +++ > > drivers/gpu/drm/i915/i915_reg.h | 9 ++ > > drivers/gpu/drm/i915/intel_device_info.c | 1 + > > drivers/gpu/drm/i915/intel_device_info.h | 5 +- > > drivers/gpu/drm/i915/intel_uncore.c | 150 +++++++++++++++++- > > drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 + > > 19 files changed, 417 insertions(+), 38 deletions(-) > >
On 03/05/2022 15:56, Matt Roper wrote: > On Tue, May 03, 2022 at 09:21:04AM +0100, Tvrtko Ursulin wrote: >> >> On 02/05/2022 17:34, Matt Roper wrote: >>> Ponte Vecchio (PVC) is a new GPU based on the Xe_HPC architecture. As a >>> compute-focused platform, PVC has compute engines and enhanced copy >>> engines, but no render engine (there is no geometry pipeline) and no >>> display. >>> >>> This is just a handful of early enablement patches, including some >>> initial support for the new copy engines (although we're not yet adding >>> those to the platform's engine list or exposing them to userspace just >>> yet). >> >> IMO lets hold off merging this until next week if that sounds acceptable? >> This week I need to do a final pull for final bits of DG2 and I would like >> to keep it as small as possible. > > I was wondering if we should try to apply patch #1 quickly, just to get > the IS_PONTEVECCHIO definition into the tree early and minimize the > cross-tree merge hassles down the road? Although I guess PVC might not > be as big a problem as some platforms since no display means that we > won't have a huge split of patches between -next and -gt-next that both > need the basic defines present. Okay, that sounds fair. Regards, Tvrtko > > > Matt > >> >> Regards, >> >> Tvrtko >> >>> >>> Ayaz A Siddiqui (1): >>> drm/i915/pvc: Define MOCS table for PVC >>> >>> John Harrison (1): >>> drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter >>> engine >>> >>> Lucas De Marchi (2): >>> drm/i915/pvc: skip all copy engines from aux table invalidate >>> drm/i915/pvc: read fuses for link copy engines >>> >>> Matt Roper (5): >>> drm/i915/pvc: Add forcewake support >>> drm/i915/pvc: Read correct RP_STATE_CAP register >>> drm/i915/pvc: Engines definitions for new copy engines >>> drm/i915/pvc: Interrupt support for new copy engines >>> drm/i915/pvc: Reset support for new copy engines >>> >>> Stuart Summers (2): >>> drm/i915/pvc: add initial Ponte Vecchio definitions >>> drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL >>> >>> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 20 ++- >>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 92 +++++++++++ >>> drivers/gpu/drm/i915/gt/intel_engine_types.h | 10 +- >>> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 12 +- >>> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 16 ++ >>> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 56 ++++--- >>> drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 + >>> drivers/gpu/drm/i915/gt/intel_mocs.c | 24 ++- >>> drivers/gpu/drm/i915/gt/intel_rps.c | 4 +- >>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 13 +- >>> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 9 +- >>> drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +- >>> drivers/gpu/drm/i915/i915_drv.h | 6 + >>> drivers/gpu/drm/i915/i915_pci.c | 23 +++ >>> drivers/gpu/drm/i915/i915_reg.h | 9 ++ >>> drivers/gpu/drm/i915/intel_device_info.c | 1 + >>> drivers/gpu/drm/i915/intel_device_info.h | 5 +- >>> drivers/gpu/drm/i915/intel_uncore.c | 150 +++++++++++++++++- >>> drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 + >>> 19 files changed, 417 insertions(+), 38 deletions(-) >>> >
Ponte Vecchio (PVC) is a new GPU based on the Xe_HPC architecture. As a compute-focused platform, PVC has compute engines and enhanced copy engines, but no render engine (there is no geometry pipeline) and no display. This is just a handful of early enablement patches, including some initial support for the new copy engines (although we're not yet adding those to the platform's engine list or exposing them to userspace just yet). Ayaz A Siddiqui (1): drm/i915/pvc: Define MOCS table for PVC John Harrison (1): drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter engine Lucas De Marchi (2): drm/i915/pvc: skip all copy engines from aux table invalidate drm/i915/pvc: read fuses for link copy engines Matt Roper (5): drm/i915/pvc: Add forcewake support drm/i915/pvc: Read correct RP_STATE_CAP register drm/i915/pvc: Engines definitions for new copy engines drm/i915/pvc: Interrupt support for new copy engines drm/i915/pvc: Reset support for new copy engines Stuart Summers (2): drm/i915/pvc: add initial Ponte Vecchio definitions drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 20 ++- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 92 +++++++++++ drivers/gpu/drm/i915/gt/intel_engine_types.h | 10 +- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 12 +- drivers/gpu/drm/i915/gt/intel_gt_irq.c | 16 ++ drivers/gpu/drm/i915/gt/intel_gt_regs.h | 56 ++++--- drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 + drivers/gpu/drm/i915/gt/intel_mocs.c | 24 ++- drivers/gpu/drm/i915/gt/intel_rps.c | 4 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 13 +- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 9 +- drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 6 + drivers/gpu/drm/i915/i915_pci.c | 23 +++ drivers/gpu/drm/i915/i915_reg.h | 9 ++ drivers/gpu/drm/i915/intel_device_info.c | 1 + drivers/gpu/drm/i915/intel_device_info.h | 5 +- drivers/gpu/drm/i915/intel_uncore.c | 150 +++++++++++++++++- drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 + 19 files changed, 417 insertions(+), 38 deletions(-)