| Message ID | 20220503102345.22817-8-nancy.lin@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add MediaTek SoC DRM (vdosys1) support for mt8195 | expand |
Hi, Nancy: On Tue, 2022-05-03 at 18:23 +0800, Nancy.Lin wrote: > Add four mmsys config APIs. The config APIs are used for config > mmsys reg. Some mmsys regs need to be set according to the > HW engine binding to the mmsys simultaneously. > > 1. mtk_mmsys_merge_async_config: config merge async width/height. > async is used for cross-clock domain synchronization. > 2. mtk_mmsys_hdr_confing: config hdr backend async width/height. > 3. mtk_mmsys_mixer_in_config and mtk_mmsys_mixer_in_config: > config mixer related settings. Reviewed-by: CK Hu <ck.hu@mediatek.com> > > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com> > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > --- > drivers/soc/mediatek/mt8195-mmsys.h | 6 +++++ > drivers/soc/mediatek/mtk-mmsys.c | 35 > ++++++++++++++++++++++++++ > include/linux/soc/mediatek/mtk-mmsys.h | 9 +++++++ > 3 files changed, 50 insertions(+) > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h > b/drivers/soc/mediatek/mt8195-mmsys.h > index fd7b455bd675..454944a9409c 100644 > --- a/drivers/soc/mediatek/mt8195-mmsys.h > +++ b/drivers/soc/mediatek/mt8195-mmsys.h > @@ -75,6 +75,12 @@ > #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << > 16) > #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE > (3 << 16) > > +#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD > 0xe30 > +#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD > 0xe70 > +#define MT8195_VDO1_HDR_TOP_CFG > 0xd00 > +#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30 > +#define MT8195_VDO1_MIXER_IN1_PAD 0xd40 > + > #define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04 > #define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 > 1 > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c > b/drivers/soc/mediatek/mtk-mmsys.c > index 3e2e5e3f721d..199503dd544a 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -228,6 +228,41 @@ void mtk_mmsys_ddp_disconnect(struct device > *dev, > } > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); > > +void mtk_mmsys_merge_async_config(struct device *dev, int idx, int > width, int height) > +{ > + mtk_mmsys_write_reg(dev_get_drvdata(dev), > MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx, > + ~0, height << 16 | width); > +} > +EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config); > + > +void mtk_mmsys_hdr_confing(struct device *dev, int be_width, int > be_height) > +{ > + mtk_mmsys_write_reg(dev_get_drvdata(dev), > MT8195_VDO1_HDRBE_ASYNC_CFG_WD, ~0, > + be_height << 16 | be_width); > +} > +EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_confing); > + > +void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool > alpha_sel, u16 alpha, > + u8 mode, u32 biwidth) > +{ > + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); > + > + mtk_mmsys_write_reg(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - > 1) * 4, ~0, > + alpha << 16 | alpha); > + mtk_mmsys_write_reg(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + > idx), > + alpha_sel << (19 + idx)); > + mtk_mmsys_write_reg(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - > 1) * 4, > + GENMASK(31, 16) | GENMASK(1, 0), biwidth << > 16 | mode); > +} > +EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config); > + > +void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, > bool channel_swap) > +{ > + mtk_mmsys_write_reg(dev_get_drvdata(dev), > MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4, > + BIT(4), channel_swap << 4); > +} > +EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap); > + > static int mtk_mmsys_reset_update(struct reset_controller_dev > *rcdev, unsigned long id, > bool assert) > { > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h > b/include/linux/soc/mediatek/mtk-mmsys.h > index b4388ba43341..fe620929b0f9 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -73,4 +73,13 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, > enum mtk_ddp_comp_id cur, > enum mtk_ddp_comp_id next); > > +void mtk_mmsys_merge_async_config(struct device *dev, int idx, int > width, int height); > + > +void mtk_mmsys_hdr_confing(struct device *dev, int be_width, int > be_height); > + > +void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool > alpha_sel, u16 alpha, > + u8 mode, u32 biwidth); > + > +void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, > bool channel_swap); > + > #endif /* __MTK_MMSYS_H */
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h index fd7b455bd675..454944a9409c 100644 --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -75,6 +75,12 @@ #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16) #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16) +#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30 +#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70 +#define MT8195_VDO1_HDR_TOP_CFG 0xd00 +#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30 +#define MT8195_VDO1_MIXER_IN1_PAD 0xd40 + #define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04 #define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1 diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 3e2e5e3f721d..199503dd544a 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -228,6 +228,41 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); +void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height) +{ + mtk_mmsys_write_reg(dev_get_drvdata(dev), MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx, + ~0, height << 16 | width); +} +EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config); + +void mtk_mmsys_hdr_confing(struct device *dev, int be_width, int be_height) +{ + mtk_mmsys_write_reg(dev_get_drvdata(dev), MT8195_VDO1_HDRBE_ASYNC_CFG_WD, ~0, + be_height << 16 | be_width); +} +EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_confing); + +void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha, + u8 mode, u32 biwidth) +{ + struct mtk_mmsys *mmsys = dev_get_drvdata(dev); + + mtk_mmsys_write_reg(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4, ~0, + alpha << 16 | alpha); + mtk_mmsys_write_reg(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx), + alpha_sel << (19 + idx)); + mtk_mmsys_write_reg(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4, + GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode); +} +EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config); + +void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap) +{ + mtk_mmsys_write_reg(dev_get_drvdata(dev), MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4, + BIT(4), channel_swap << 4); +} +EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap); + static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index b4388ba43341..fe620929b0f9 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -73,4 +73,13 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next); +void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height); + +void mtk_mmsys_hdr_confing(struct device *dev, int be_width, int be_height); + +void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha, + u8 mode, u32 biwidth); + +void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap); + #endif /* __MTK_MMSYS_H */