On Sun, May 8, 2022 at 10:56 AM Jonathan Cameron <jic23@kernel.org> wrote: > > From: Jonathan Cameron <Jonathan.Cameron@huawei.com> > > ____cacheline_aligned is an insufficient guarantee for non-coherent DMA > on platforms with 128 byte cachelines above L1. Switch to the updated > IIO_DMA_MINALIGN definition. > > Fixes: 1b791fadf3a1 ("iio: dac: mcp4902/mcp4912/mcp4922 dac driver") > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > Cc: Michael Welling <mwelling@ieee.org> > Acked-by: Nuno Sá <nuno.sa@analog.com> > --- > drivers/iio/dac/mcp4922.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/iio/dac/mcp4922.c b/drivers/iio/dac/mcp4922.c > index cb9e60e71b91..6c0e31032c57 100644 > --- a/drivers/iio/dac/mcp4922.c > +++ b/drivers/iio/dac/mcp4922.c > @@ -29,7 +29,7 @@ struct mcp4922_state { > unsigned int value[MCP4922_NUM_CHANNELS]; > unsigned int vref_mv; > struct regulator *vref_reg; > - u8 mosi[2] ____cacheline_aligned; > + u8 mosi[2] __aligned(IIO_DMA_MINALIGN); Acked-by: Michael Welling <mwelling@ieee.org> > }; > > #define MCP4922_CHAN(chan, bits) { \ > -- > 2.36.0 >
diff --git a/drivers/iio/dac/mcp4922.c b/drivers/iio/dac/mcp4922.c index cb9e60e71b91..6c0e31032c57 100644 --- a/drivers/iio/dac/mcp4922.c +++ b/drivers/iio/dac/mcp4922.c @@ -29,7 +29,7 @@ struct mcp4922_state { unsigned int value[MCP4922_NUM_CHANNELS]; unsigned int vref_mv; struct regulator *vref_reg; - u8 mosi[2] ____cacheline_aligned; + u8 mosi[2] __aligned(IIO_DMA_MINALIGN); }; #define MCP4922_CHAN(chan, bits) { \