diff mbox series

drm/amdgpu: clean up some inconsistent indenting

Message ID 20220510060440.67178-1-jiapeng.chong@linux.alibaba.com (mailing list archive)
State New, archived
Headers show
Series drm/amdgpu: clean up some inconsistent indenting | expand

Commit Message

Jiapeng Chong May 10, 2022, 6:04 a.m. UTC
Eliminate the follow smatch warning:

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c:35 nbio_v7_7_get_rev_id() warn:
inconsistent indenting.

drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c:214 nbio_v7_7_init_registers()
warn: inconsistent indenting.

Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
---
 drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

Comments

Alex Deucher May 10, 2022, 3:09 p.m. UTC | #1
Applied.  Thanks!

Alex

On Tue, May 10, 2022 at 2:05 AM Jiapeng Chong
<jiapeng.chong@linux.alibaba.com> wrote:
>
> Eliminate the follow smatch warning:
>
> drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c:35 nbio_v7_7_get_rev_id() warn:
> inconsistent indenting.
>
> drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c:214 nbio_v7_7_init_registers()
> warn: inconsistent indenting.
>
> Reported-by: Abaci Robot <abaci@linux.alibaba.com>
> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c | 17 ++++++++---------
>  1 file changed, 8 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
> index e32c874b42b5..cdc0c9779848 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
> @@ -32,8 +32,7 @@ static u32 nbio_v7_7_get_rev_id(struct amdgpu_device *adev)
>  {
>         u32 tmp;
>
> -               tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
> -
> +       tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
>         tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
>         tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
>
> @@ -211,14 +210,14 @@ static void nbio_v7_7_init_registers(struct amdgpu_device *adev)
>  {
>         uint32_t def, data;
>
> -               def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3);
> -               data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
> -                       CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
> -               data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
> -                       CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
> +       def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3);
> +       data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
> +                            CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
> +       data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
> +                            CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
>
> -               if (def != data)
> -                       WREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3, data);
> +       if (def != data)
> +               WREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3, data);
>
>  }
>
> --
> 2.20.1.7.g153144c
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
index e32c874b42b5..cdc0c9779848 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
@@ -32,8 +32,7 @@  static u32 nbio_v7_7_get_rev_id(struct amdgpu_device *adev)
 {
 	u32 tmp;
 
-		tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
-
+	tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
 	tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
 	tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
 
@@ -211,14 +210,14 @@  static void nbio_v7_7_init_registers(struct amdgpu_device *adev)
 {
 	uint32_t def, data;
 
-		def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3);
-		data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
-			CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
-		data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
-			CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
+	def = data = RREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3);
+	data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
+			     CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
+	data = REG_SET_FIELD(data, BIF0_PCIE_MST_CTRL_3,
+			     CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
 
-		if (def != data)
-			WREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3, data);
+	if (def != data)
+		WREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3, data);
 
 }