| Message ID | 20220513084754.10601-1-nirmoy.das@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3] drm/i915: Enable Tile4 tiling mode | expand |
On 5/13/2022 1:01 PM, Patchwork wrote: > Project List - Patchwork *Patch Details* > *Series:* drm/i915: Enable Tile4 tiling mode (rev3) > *URL:* https://patchwork.freedesktop.org/series/103881/ > *State:* failure > *Details:* > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/index.html > > > CI Bug Log - changes from CI_DRM_11646_full -> Patchwork_103881v3_full > > > Summary > > *FAILURE* > > Serious unknown changes coming with Patchwork_103881v3_full absolutely > need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_103881v3_full, please notify your bug team to > allow them > to document this new failure mode, which will reduce false positives > in CI. > > > Participating hosts (11 -> 11) > > No changes in participating hosts > > > Possible new issues > > Here are the unknown changes that may have been introduced in > Patchwork_103881v3_full: > > > IGT changes > > > Possible regressions > > * igt@kms_cursor_crc@pipe-a-cursor-dpms: > o shard-tglb: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-tglb3/igt@kms_cursor_crc@pipe-a-cursor-dpms.html> > -> INCOMPLETE > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb8/igt@kms_cursor_crc@pipe-a-cursor-dpms.html> > This is unrelated as this patch only changes igt@i915_selftest@live@client Regards, Nirmoy > * > > > Known issues > > Here are the changes found in Patchwork_103881v3_full that come from > known issues: > > > IGT changes > > > Issues hit > > * > > igt@gem_exec_fair@basic-deadline: > > o shard-kbl: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-kbl6/igt@gem_exec_fair@basic-deadline.html> > -> FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-kbl6/igt@gem_exec_fair@basic-deadline.html> > (i915#2846 <https://gitlab.freedesktop.org/drm/intel/issues/2846>) > * > > igt@gem_exec_fair@basic-none@vcs0: > > o shard-apl: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-apl4/igt@gem_exec_fair@basic-none@vcs0.html> > -> FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl8/igt@gem_exec_fair@basic-none@vcs0.html> > (i915#2842 <https://gitlab.freedesktop.org/drm/intel/issues/2842>) > * > > igt@gem_exec_fair@basic-pace@vecs0: > > o shard-glk: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-glk6/igt@gem_exec_fair@basic-pace@vecs0.html> > -> FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-glk1/igt@gem_exec_fair@basic-pace@vecs0.html> > (i915#2842 > <https://gitlab.freedesktop.org/drm/intel/issues/2842>) +2 > similar issues > * > > igt@gem_exec_flush@basic-batch-kernel-default-wb: > > o shard-snb: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-snb7/igt@gem_exec_flush@basic-batch-kernel-default-wb.html> > -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-snb6/igt@gem_exec_flush@basic-batch-kernel-default-wb.html> > (fdo#109271 > <https://bugs.freedesktop.org/show_bug.cgi?id=109271>) +3 > similar issues > * > > igt@gem_lmem_swapping@heavy-random: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@gem_lmem_swapping@heavy-random.html> > (i915#4613 <https://gitlab.freedesktop.org/drm/intel/issues/4613>) > * > > igt@gem_lmem_swapping@heavy-verify-random: > > o > > shard-kbl: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-kbl4/igt@gem_lmem_swapping@heavy-verify-random.html> > (fdo#109271 > <https://bugs.freedesktop.org/show_bug.cgi?id=109271> / > i915#4613 <https://gitlab.freedesktop.org/drm/intel/issues/4613>) > > o > > shard-skl: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-skl8/igt@gem_lmem_swapping@heavy-verify-random.html> > (fdo#109271 > <https://bugs.freedesktop.org/show_bug.cgi?id=109271> / > i915#4613 > <https://gitlab.freedesktop.org/drm/intel/issues/4613>) +2 > similar issues > > * > > igt@gem_pwrite@basic-exhaustion: > > o shard-apl: NOTRUN -> WARN > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl1/igt@gem_pwrite@basic-exhaustion.html> > (i915#2658 <https://gitlab.freedesktop.org/drm/intel/issues/2658>) > * > > igt@gem_pxp@display-protected-crc: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@gem_pxp@display-protected-crc.html> > (i915#4270 <https://gitlab.freedesktop.org/drm/intel/issues/4270>) > * > > igt@gem_userptr_blits@unsync-overlap: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@gem_userptr_blits@unsync-overlap.html> > (i915#3297 <https://gitlab.freedesktop.org/drm/intel/issues/3297>) > * > > igt@gen9_exec_parse@allowed-single: > > o shard-glk: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-glk4/igt@gen9_exec_parse@allowed-single.html> > -> DMESG-WARN > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-glk1/igt@gen9_exec_parse@allowed-single.html> > (i915#5566 > <https://gitlab.freedesktop.org/drm/intel/issues/5566> / > i915#716 <https://gitlab.freedesktop.org/drm/intel/issues/716>) > * > > igt@gen9_exec_parse@bb-start-cmd: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@gen9_exec_parse@bb-start-cmd.html> > (i915#2527 > <https://gitlab.freedesktop.org/drm/intel/issues/2527> / > i915#2856 <https://gitlab.freedesktop.org/drm/intel/issues/2856>) > * > > igt@i915_pm_dc@dc3co-vpb-simulation: > > o shard-iclb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb3/igt@i915_pm_dc@dc3co-vpb-simulation.html> > (i915#658 <https://gitlab.freedesktop.org/drm/intel/issues/658>) > * > > igt@i915_pm_rpm@modeset-non-lpsp: > > o shard-iclb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb3/igt@i915_pm_rpm@modeset-non-lpsp.html> > (fdo#110892 <https://bugs.freedesktop.org/show_bug.cgi?id=110892>) > * > > igt@i915_pm_rpm@modeset-pc8-residency-stress: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@i915_pm_rpm@modeset-pc8-residency-stress.html> > (fdo#109506 > <https://bugs.freedesktop.org/show_bug.cgi?id=109506> / > i915#2411 <https://gitlab.freedesktop.org/drm/intel/issues/2411>) > * > > igt@i915_pm_sseu@full-enable: > > o shard-iclb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb3/igt@i915_pm_sseu@full-enable.html> > (i915#4387 <https://gitlab.freedesktop.org/drm/intel/issues/4387>) > * > > igt@i915_query@query-topology-unsupported: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@i915_query@query-topology-unsupported.html> > (fdo#109302 <https://bugs.freedesktop.org/show_bug.cgi?id=109302>) > * > > igt@i915_suspend@fence-restore-tiled2untiled: > > o shard-glk: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-glk1/igt@i915_suspend@fence-restore-tiled2untiled.html> > -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-glk3/igt@i915_suspend@fence-restore-tiled2untiled.html> > (fdo#109271 <https://bugs.freedesktop.org/show_bug.cgi?id=109271>) > * > > igt@kms_atomic_transition@plane-all-modeset-transition: > > o shard-iclb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb3/igt@kms_atomic_transition@plane-all-modeset-transition.html> > (i915#1769 <https://gitlab.freedesktop.org/drm/intel/issues/1769>) > * > > igt@kms_big_fb@4-tiled-addfb-size-offset-overflow: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html> > (i915#5286 > <https://gitlab.freedesktop.org/drm/intel/issues/5286>) +1 > similar issue > * > > igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0: > > o shard-apl: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html> > (fdo#109271 > <https://bugs.freedesktop.org/show_bug.cgi?id=109271>) +53 > similar issues > * > > igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip: > > o shard-iclb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html> > (fdo#110723 > <https://bugs.freedesktop.org/show_bug.cgi?id=110723>) +1 > similar issue > * > > igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html> > (i915#3689 > <https://gitlab.freedesktop.org/drm/intel/issues/3689> / > i915#3886 > <https://gitlab.freedesktop.org/drm/intel/issues/3886>) +1 > similar issue > * > > igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc: > > o shard-apl: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl8/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html> > (fdo#109271 > <https://bugs.freedesktop.org/show_bug.cgi?id=109271> / > i915#3886 > <https://gitlab.freedesktop.org/drm/intel/issues/3886>) +2 > similar issues > * > > igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs: > > o shard-kbl: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-kbl4/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html> > (fdo#109271 > <https://bugs.freedesktop.org/show_bug.cgi?id=109271> / > i915#3886 > <https://gitlab.freedesktop.org/drm/intel/issues/3886>) +2 > similar issues > * > > igt@kms_ccs@pipe-d-bad-rotation-90-y_tiled_gen12_mc_ccs: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@kms_ccs@pipe-d-bad-rotation-90-y_tiled_gen12_mc_ccs.html> > (i915#3689 <https://gitlab.freedesktop.org/drm/intel/issues/3689>) > * > > igt@kms_chamelium@dp-hpd-storm-disable: > > o shard-skl: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-skl6/igt@kms_chamelium@dp-hpd-storm-disable.html> > (fdo#109271 > <https://bugs.freedesktop.org/show_bug.cgi?id=109271> / > fdo#111827 > <https://bugs.freedesktop.org/show_bug.cgi?id=111827>) +7 > similar issues > * > > igt@kms_chamelium@vga-hpd-after-suspend: > > o shard-iclb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb3/igt@kms_chamelium@vga-hpd-after-suspend.html> > (fdo#109284 > <https://bugs.freedesktop.org/show_bug.cgi?id=109284> / > fdo#111827 > <https://bugs.freedesktop.org/show_bug.cgi?id=111827>) +2 > similar issues > * > > igt@kms_chamelium@vga-hpd-with-enabled-mode: > > o shard-snb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-snb4/igt@kms_chamelium@vga-hpd-with-enabled-mode.html> > (fdo#109271 > <https://bugs.freedesktop.org/show_bug.cgi?id=109271> / > fdo#111827 > <https://bugs.freedesktop.org/show_bug.cgi?id=111827>) +1 > similar issue > * > > igt@kms_color@pipe-d-ctm-0-5: > > o shard-skl: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-skl8/igt@kms_color@pipe-d-ctm-0-5.html> > (fdo#109271 > <https://bugs.freedesktop.org/show_bug.cgi?id=109271>) +74 > similar issues > * > > igt@kms_color_chamelium@pipe-a-ctm-negative: > > o shard-apl: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl1/igt@kms_color_chamelium@pipe-a-ctm-negative.html> > (fdo#109271 > <https://bugs.freedesktop.org/show_bug.cgi?id=109271> / > fdo#111827 > <https://bugs.freedesktop.org/show_bug.cgi?id=111827>) +1 > similar issue > * > > igt@kms_color_chamelium@pipe-b-ctm-max: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@kms_color_chamelium@pipe-b-ctm-max.html> > (fdo#109284 > <https://bugs.freedesktop.org/show_bug.cgi?id=109284> / > fdo#111827 > <https://bugs.freedesktop.org/show_bug.cgi?id=111827>) +3 > similar issues > * > > igt@kms_color_chamelium@pipe-c-ctm-max: > > o shard-kbl: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-kbl4/igt@kms_color_chamelium@pipe-c-ctm-max.html> > (fdo#109271 > <https://bugs.freedesktop.org/show_bug.cgi?id=109271> / > fdo#111827 > <https://bugs.freedesktop.org/show_bug.cgi?id=111827>) +2 > similar issues > * > > igt@kms_content_protection@lic: > > o shard-kbl: NOTRUN -> TIMEOUT > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-kbl4/igt@kms_content_protection@lic.html> > (i915#1319 <https://gitlab.freedesktop.org/drm/intel/issues/1319>) > * > > igt@kms_cursor_crc@pipe-a-cursor-32x32-rapid-movement: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@kms_cursor_crc@pipe-a-cursor-32x32-rapid-movement.html> > (i915#3319 > <https://gitlab.freedesktop.org/drm/intel/issues/3319>) +1 > similar issue > * > > igt@kms_cursor_crc@pipe-a-cursor-max-size-random: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@kms_cursor_crc@pipe-a-cursor-max-size-random.html> > (i915#3359 > <https://gitlab.freedesktop.org/drm/intel/issues/3359>) +1 > similar issue > * > > igt@kms_cursor_crc@pipe-a-cursor-max-size-sliding: > > o shard-iclb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb3/igt@kms_cursor_crc@pipe-a-cursor-max-size-sliding.html> > (fdo#109278 > <https://bugs.freedesktop.org/show_bug.cgi?id=109278>) +9 > similar issues > * > > igt@kms_cursor_crc@pipe-b-cursor-32x10-random: > > o shard-kbl: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-kbl4/igt@kms_cursor_crc@pipe-b-cursor-32x10-random.html> > (fdo#109271 > <https://bugs.freedesktop.org/show_bug.cgi?id=109271>) +27 > similar issues > * > > igt@kms_cursor_crc@pipe-b-cursor-512x170-sliding: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@kms_cursor_crc@pipe-b-cursor-512x170-sliding.html> > (fdo#109279 > <https://bugs.freedesktop.org/show_bug.cgi?id=109279> / > i915#3359 <https://gitlab.freedesktop.org/drm/intel/issues/3359>) > * > > igt@kms_cursor_legacy@flip-vs-cursor-legacy: > > o shard-skl: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html> > -> FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html> > (i915#2346 <https://gitlab.freedesktop.org/drm/intel/issues/2346>) > * > > igt@kms_draw_crc@draw-method-rgb565-pwrite-4tiled: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@kms_draw_crc@draw-method-rgb565-pwrite-4tiled.html> > (i915#5287 <https://gitlab.freedesktop.org/drm/intel/issues/5287>) > * > > igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-4tiled: > > o shard-iclb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb3/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-4tiled.html> > (i915#5287 <https://gitlab.freedesktop.org/drm/intel/issues/5287>) > * > > igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html> > (fdo#109274 > <https://bugs.freedesktop.org/show_bug.cgi?id=109274> / > fdo#111825 <https://bugs.freedesktop.org/show_bug.cgi?id=111825>) > * > > igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2: > > o shard-glk: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html> > -> FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html> > (i915#79 <https://gitlab.freedesktop.org/drm/intel/issues/79>) > * > > igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: > > o shard-kbl: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html> > -> DMESG-WARN > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html> > (i915#180 > <https://gitlab.freedesktop.org/drm/intel/issues/180>) +8 > similar issues > * > > igt@kms_flip@flip-vs-suspend-interruptible@c-edp1: > > o shard-skl: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-skl6/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html> > -> INCOMPLETE > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-skl6/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html> > (i915#4939 <https://gitlab.freedesktop.org/drm/intel/issues/4939>) > * > > igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1: > > o shard-skl: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-skl9/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html> > -> FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-skl7/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html> > (i915#2122 > <https://gitlab.freedesktop.org/drm/intel/issues/2122>) +3 > similar issues > * > > igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html> > (i915#2587 <https://gitlab.freedesktop.org/drm/intel/issues/2587>) > * > > igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling: > > o shard-iclb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html> > (i915#2587 <https://gitlab.freedesktop.org/drm/intel/issues/2587>) > * > > igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu: > > o shard-iclb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu.html> > (fdo#109280 > <https://bugs.freedesktop.org/show_bug.cgi?id=109280>) +1 > similar issue > * > > igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-pwrite: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-pwrite.html> > (fdo#109280 > <https://bugs.freedesktop.org/show_bug.cgi?id=109280> / > fdo#111825 > <https://bugs.freedesktop.org/show_bug.cgi?id=111825>) +5 > similar issues > * > > igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes: > > o shard-iclb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb3/igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes.html> > (fdo#109289 <https://bugs.freedesktop.org/show_bug.cgi?id=109289>) > * > > igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes: > > o shard-apl: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html> > -> DMESG-WARN > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html> > (i915#180 > <https://gitlab.freedesktop.org/drm/intel/issues/180>) +4 > similar issues > * > > igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: > > o shard-apl: NOTRUN -> FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl1/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html> > (fdo#108145 > <https://bugs.freedesktop.org/show_bug.cgi?id=108145> / > i915#265 > <https://gitlab.freedesktop.org/drm/intel/issues/265>) +1 > similar issue > * > > igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: > > o shard-skl: NOTRUN -> FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html> > (fdo#108145 > <https://bugs.freedesktop.org/show_bug.cgi?id=108145> / > i915#265 <https://gitlab.freedesktop.org/drm/intel/issues/265>) > * > > igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: > > o shard-skl: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html> > -> FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html> > (fdo#108145 > <https://bugs.freedesktop.org/show_bug.cgi?id=108145> / > i915#265 <https://gitlab.freedesktop.org/drm/intel/issues/265>) > * > > igt@kms_plane_lowres@pipe-b-tiling-none: > > o shard-iclb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb3/igt@kms_plane_lowres@pipe-b-tiling-none.html> > (i915#3536 <https://gitlab.freedesktop.org/drm/intel/issues/3536>) > * > > igt@kms_plane_lowres@pipe-d-tiling-4: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@kms_plane_lowres@pipe-d-tiling-4.html> > (i915#5288 <https://gitlab.freedesktop.org/drm/intel/issues/5288>) > * > > igt@kms_plane_multiple@atomic-pipe-b-tiling-yf: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html> > (fdo#111615 > <https://bugs.freedesktop.org/show_bug.cgi?id=111615>) +2 > similar issues > * > > igt@kms_plane_scaling@downscale-with-modifier-factor-0-5@pipe-c-edp-1-downscale-with-modifier: > > o shard-iclb: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-iclb7/igt@kms_plane_scaling@downscale-with-modifier-factor-0-5@pipe-c-edp-1-downscale-with-modifier.html> > -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb2/igt@kms_plane_scaling@downscale-with-modifier-factor-0-5@pipe-c-edp-1-downscale-with-modifier.html> > (i915#5176 > <https://gitlab.freedesktop.org/drm/intel/issues/5176>) +2 > similar issues > * > > igt@kms_psr2_sf@overlay-plane-move-continuous-sf: > > o shard-kbl: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-kbl4/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html> > (fdo#109271 > <https://bugs.freedesktop.org/show_bug.cgi?id=109271> / > i915#658 <https://gitlab.freedesktop.org/drm/intel/issues/658>) > * > > igt@kms_psr2_sf@overlay-plane-update-continuous-sf: > > o shard-apl: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl7/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html> > (fdo#109271 > <https://bugs.freedesktop.org/show_bug.cgi?id=109271> / > i915#658 <https://gitlab.freedesktop.org/drm/intel/issues/658>) > * > > igt@kms_psr@psr2_primary_mmap_cpu: > > o shard-iclb: PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html> > -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb7/igt@kms_psr@psr2_primary_mmap_cpu.html> > (fdo#109441 > <https://bugs.freedesktop.org/show_bug.cgi?id=109441>) +2 > similar issues > * > > igt@kms_setmode@basic-clone-single-crtc: > > o shard-iclb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb3/igt@kms_setmode@basic-clone-single-crtc.html> > (i915#3555 <https://gitlab.freedesktop.org/drm/intel/issues/3555>) > * > > igt@kms_writeback@writeback-fb-id: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@kms_writeback@writeback-fb-id.html> > (i915#2437 <https://gitlab.freedesktop.org/drm/intel/issues/2437>) > * > > igt@nouveau_crc@pipe-c-source-outp-inactive: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@nouveau_crc@pipe-c-source-outp-inactive.html> > (i915#2530 <https://gitlab.freedesktop.org/drm/intel/issues/2530>) > * > > igt@perf@polling: > > o shard-snb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-snb4/igt@perf@polling.html> > (fdo#109271 > <https://bugs.freedesktop.org/show_bug.cgi?id=109271>) +46 > similar issues > * > > igt@prime_nv_pcopy@test3_1: > > o shard-iclb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb3/igt@prime_nv_pcopy@test3_1.html> > (fdo#109291 <https://bugs.freedesktop.org/show_bug.cgi?id=109291>) > * > > igt@prime_nv_test@i915_nv_sharing: > > o shard-tglb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@prime_nv_test@i915_nv_sharing.html> > (fdo#109291 <https://bugs.freedesktop.org/show_bug.cgi?id=109291>) > * > > igt@prime_vgem@fence-write-hang: > > o shard-iclb: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb3/igt@prime_vgem@fence-write-hang.html> > (fdo#109295 <https://bugs.freedesktop.org/show_bug.cgi?id=109295>) > * > > igt@syncobj_timeline@invalid-transfer-non-existent-point: > > o shard-apl: NOTRUN -> DMESG-WARN > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl8/igt@syncobj_timeline@invalid-transfer-non-existent-point.html> > (i915#5098 <https://gitlab.freedesktop.org/drm/intel/issues/5098>) > * > > igt@sysfs_clients@fair-3: > > o shard-apl: NOTRUN -> SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl8/igt@sysfs_clients@fair-3.html> > (fdo#109271 > <https://bugs.freedesktop.org/show_bug.cgi?id=109271> / > i915#2994 <https://gitlab.freedesktop.org/drm/intel/issues/2994>) > > > Possible fixes > > * > > igt@gem_ctx_isolation@preservation-s3@bcs0: > > o shard-skl: INCOMPLETE > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-skl6/igt@gem_ctx_isolation@preservation-s3@bcs0.html> > (i915#4793 > <https://gitlab.freedesktop.org/drm/intel/issues/4793>) -> > PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-skl8/igt@gem_ctx_isolation@preservation-s3@bcs0.html> > * > > igt@gem_exec_fair@basic-pace-share@rcs0: > > o shard-tglb: FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html> > (i915#2842 > <https://gitlab.freedesktop.org/drm/intel/issues/2842>) -> > PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html> > * > > igt@gem_exec_fair@basic-throttle@rcs0: > > o shard-glk: FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-glk4/igt@gem_exec_fair@basic-throttle@rcs0.html> > (i915#2842 > <https://gitlab.freedesktop.org/drm/intel/issues/2842>) -> > PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html> > * > > igt@gem_exec_whisper@basic-fds-forked-all: > > o {shard-tglu}: INCOMPLETE > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-tglu-6/igt@gem_exec_whisper@basic-fds-forked-all.html> > (i915#5966 > <https://gitlab.freedesktop.org/drm/intel/issues/5966>) -> > PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglu-3/igt@gem_exec_whisper@basic-fds-forked-all.html> > * > > igt@i915_suspend@debugfs-reader: > > o shard-skl: INCOMPLETE > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-skl7/igt@i915_suspend@debugfs-reader.html> > (i915#4939 > <https://gitlab.freedesktop.org/drm/intel/issues/4939>) -> > PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-skl6/igt@i915_suspend@debugfs-reader.html> > * > > igt@i915_suspend@forcewake: > > o shard-skl: INCOMPLETE > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-skl8/igt@i915_suspend@forcewake.html> > (i915#4817 > <https://gitlab.freedesktop.org/drm/intel/issues/4817>) -> > PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-skl10/igt@i915_suspend@forcewake.html> > * > > igt@kms_cursor_crc@pipe-a-cursor-suspend: > > o shard-snb: INCOMPLETE > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-snb6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html> > -> PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-snb4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html> > * > > igt@kms_fbcon_fbt@fbc-suspend: > > o shard-apl: INCOMPLETE > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html> > (i915#180 > <https://gitlab.freedesktop.org/drm/intel/issues/180> / > i915#1982 > <https://gitlab.freedesktop.org/drm/intel/issues/1982>) -> > PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html> > * > > igt@kms_flip@2x-flip-vs-wf_vblank@ab-hdmi-a1-hdmi-a2: > > o shard-glk: FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-glk1/igt@kms_flip@2x-flip-vs-wf_vblank@ab-hdmi-a1-hdmi-a2.html> > (i915#2122 > <https://gitlab.freedesktop.org/drm/intel/issues/2122>) -> > PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-glk2/igt@kms_flip@2x-flip-vs-wf_vblank@ab-hdmi-a1-hdmi-a2.html> > * > > igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: > > o shard-apl: DMESG-WARN > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html> > (i915#180 > <https://gitlab.freedesktop.org/drm/intel/issues/180>) -> PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html> > +3 similar issues > * > > igt@kms_flip@flip-vs-suspend@a-dp1: > > o shard-kbl: DMESG-WARN > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-kbl6/igt@kms_flip@flip-vs-suspend@a-dp1.html> > (i915#180 > <https://gitlab.freedesktop.org/drm/intel/issues/180>) -> PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-kbl4/igt@kms_flip@flip-vs-suspend@a-dp1.html> > +1 similar issue > * > > igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes: > > o shard-tglb: INCOMPLETE > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-tglb5/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html> > -> PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html> > * > > igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale: > > o shard-iclb: SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html> > (i915#5235 > <https://gitlab.freedesktop.org/drm/intel/issues/5235>) -> > PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb4/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html> > +2 similar issues > * > > igt@kms_psr@psr2_no_drrs: > > o shard-iclb: SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-iclb6/igt@kms_psr@psr2_no_drrs.html> > (fdo#109441 > <https://bugs.freedesktop.org/show_bug.cgi?id=109441>) -> PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb2/igt@kms_psr@psr2_no_drrs.html> > * > > igt@kms_psr_stress_test@flip-primary-invalidate-overlay: > > o shard-tglb: SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-tglb5/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html> > (i915#5519 > <https://gitlab.freedesktop.org/drm/intel/issues/5519>) -> > PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-tglb7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html> > * > > igt@kms_psr_stress_test@invalidate-primary-flip-overlay: > > o shard-iclb: SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-iclb8/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html> > (i915#5519 > <https://gitlab.freedesktop.org/drm/intel/issues/5519>) -> > PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb8/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html> > * > > igt@perf@polling-parameterized: > > o shard-skl: FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-skl2/igt@perf@polling-parameterized.html> > (i915#5639 > <https://gitlab.freedesktop.org/drm/intel/issues/5639>) -> > PASS > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-skl10/igt@perf@polling-parameterized.html> > > > Warnings > > * > > igt@gem_exec_balancer@parallel-bb-first: > > o shard-iclb: SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-iclb6/igt@gem_exec_balancer@parallel-bb-first.html> > (i915#4525 > <https://gitlab.freedesktop.org/drm/intel/issues/4525>) -> > DMESG-WARN > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb4/igt@gem_exec_balancer@parallel-bb-first.html> > (i915#5614 <https://gitlab.freedesktop.org/drm/intel/issues/5614>) > * > > igt@gem_exec_balancer@parallel-keep-submit-fence: > > o shard-iclb: DMESG-WARN > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-iclb1/igt@gem_exec_balancer@parallel-keep-submit-fence.html> > (i915#5614 > <https://gitlab.freedesktop.org/drm/intel/issues/5614>) -> > SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb3/igt@gem_exec_balancer@parallel-keep-submit-fence.html> > (i915#4525 <https://gitlab.freedesktop.org/drm/intel/issues/4525>) > * > > igt@kms_psr2_sf@overlay-plane-move-continuous-sf: > > o shard-iclb: SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html> > (i915#2920 > <https://gitlab.freedesktop.org/drm/intel/issues/2920>) -> > SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb7/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html> > (i915#658 <https://gitlab.freedesktop.org/drm/intel/issues/658>) > * > > igt@kms_psr2_su@page_flip-p010: > > o shard-iclb: SKIP > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-iclb6/igt@kms_psr2_su@page_flip-p010.html> > (fdo#109642 > <https://bugs.freedesktop.org/show_bug.cgi?id=109642> / > fdo#111068 > <https://bugs.freedesktop.org/show_bug.cgi?id=111068> / > i915#658 > <https://gitlab.freedesktop.org/drm/intel/issues/658>) -> FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-iclb2/igt@kms_psr2_su@page_flip-p010.html> > (i915#5939 <https://gitlab.freedesktop.org/drm/intel/issues/5939>) > * > > igt@runner@aborted: > > o shard-apl: (FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-apl7/igt@runner@aborted.html>, > FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-apl1/igt@runner@aborted.html>, > FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-apl2/igt@runner@aborted.html>, > FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-apl8/igt@runner@aborted.html>, > FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-apl6/igt@runner@aborted.html>, > FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-apl8/igt@runner@aborted.html>, > FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-apl6/igt@runner@aborted.html>, > FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11646/shard-apl8/igt@runner@aborted.html>) > (fdo#109271 > <https://bugs.freedesktop.org/show_bug.cgi?id=109271> / > i915#180 <https://gitlab.freedesktop.org/drm/intel/issues/180> > / i915#3002 > <https://gitlab.freedesktop.org/drm/intel/issues/3002> / > i915#4312 > <https://gitlab.freedesktop.org/drm/intel/issues/4312> / > i915#5257 > <https://gitlab.freedesktop.org/drm/intel/issues/5257>) -> > (FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl8/igt@runner@aborted.html>, > FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl4/igt@runner@aborted.html>, > FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl6/igt@runner@aborted.html>, > FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl3/igt@runner@aborted.html>, > FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl4/igt@runner@aborted.html>, > FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl8/igt@runner@aborted.html>, > FAIL > <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v3/shard-apl8/igt@runner@aborted.html>) > (i915#180 > <https://gitlab.freedesktop.org/drm/intel/issues/180> / > i915#3002 > <https://gitlab.freedesktop.org/drm/intel/issues/3002> / > i915#4312 > <https://gitlab.freedesktop.org/drm/intel/issues/4312> / > i915#5257 <https://gitlab.freedesktop.org/drm/intel/issues/5257>) > > {name}: This element is suppressed. This means it is ignored when > computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > > Build changes > > * Linux: CI_DRM_11646 -> Patchwork_103881v3 > > CI-20190529: 20190529 > CI_DRM_11646: 8e5417afe580e2eac869c09e1454d174078523fd @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_6471: 1d6816f1200520f936a799b7b0ef2e6f396abb16 @ > https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_103881v3: 8e5417afe580e2eac869c09e1454d174078523fd @ > git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ > git://anongit.freedesktop.org/piglit >
On Fri, May 13, 2022 at 10:47:54AM +0200, Nirmoy Das wrote: > From: Bommu Krishnaiah <krishnaiah.bommu@intel.com> > > Enable Tile4 tiling mode on platform that supports > Tile4 but no TileY like DG2. Drive-by comment: the patch description doesn't match what the code is actually doing. Tile4 is already enabled on these platforms (e.g., see "drm/i915/dg2: Tile 4 plane format support"). This patch appears to just be updating selftest code, not enabling anything new. Matt > > v3: add a function to find X-tile availability for a platform. > v2: disable X-tile for iGPU in fastblit > fix checkpath --strict warnings > > Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com> > Co-developed-by: Nirmoy Das <nirmoy.das@intel.com> > Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> > --- > .../i915/gem/selftests/i915_gem_client_blt.c | 250 ++++++++++++++---- > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 ++ > 2 files changed, 227 insertions(+), 45 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c > index ddd0772fd828..3cfc621ef363 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c > @@ -6,6 +6,7 @@ > #include "i915_selftest.h" > > #include "gt/intel_context.h" > +#include "gt/intel_engine_regs.h" > #include "gt/intel_engine_user.h" > #include "gt/intel_gpu_commands.h" > #include "gt/intel_gt.h" > @@ -18,10 +19,71 @@ > #include "huge_gem_object.h" > #include "mock_context.h" > > +#define OW_SIZE 16 /* in bytes */ > +#define F_SUBTILE_SIZE 64 /* in bytes */ > +#define F_TILE_WIDTH 128 /* in bytes */ > +#define F_TILE_HEIGHT 32 /* in pixels */ > +#define F_SUBTILE_WIDTH OW_SIZE /* in bytes */ > +#define F_SUBTILE_HEIGHT 4 /* in pixels */ > + > +static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp) > +{ > + int tile_base; > + int tile_x, tile_y; > + int swizzle, subtile; > + int pixel_size = bpp / 8; > + int pos; > + > + /* > + * Subtile remapping for F tile. Note that map[a]==b implies map[b]==a > + * so we can use the same table to tile and until. > + */ > + static const u8 f_subtile_map[] = { > + 0, 1, 2, 3, 8, 9, 10, 11, > + 4, 5, 6, 7, 12, 13, 14, 15, > + 16, 17, 18, 19, 24, 25, 26, 27, > + 20, 21, 22, 23, 28, 29, 30, 31, > + 32, 33, 34, 35, 40, 41, 42, 43, > + 36, 37, 38, 39, 44, 45, 46, 47, > + 48, 49, 50, 51, 56, 57, 58, 59, > + 52, 53, 54, 55, 60, 61, 62, 63 > + }; > + > + x *= pixel_size; > + /* > + * Where does the 4k tile start (in bytes)? This is the same for Y and > + * F so we can use the Y-tile algorithm to get to that point. > + */ > + tile_base = > + y / F_TILE_HEIGHT * stride * F_TILE_HEIGHT + > + x / F_TILE_WIDTH * 4096; > + > + /* Find pixel within tile */ > + tile_x = x % F_TILE_WIDTH; > + tile_y = y % F_TILE_HEIGHT; > + > + /* And figure out the subtile within the 4k tile */ > + subtile = tile_y / F_SUBTILE_HEIGHT * 8 + tile_x / F_SUBTILE_WIDTH; > + > + /* Swizzle the subtile number according to the bspec diagram */ > + swizzle = f_subtile_map[subtile]; > + > + /* Calculate new position */ > + pos = tile_base + > + swizzle * F_SUBTILE_SIZE + > + tile_y % F_SUBTILE_HEIGHT * OW_SIZE + > + tile_x % F_SUBTILE_WIDTH; > + > + GEM_BUG_ON(!IS_ALIGNED(pos, pixel_size)); > + > + return pos / pixel_size * 4; > +} > + > enum client_tiling { > CLIENT_TILING_LINEAR, > CLIENT_TILING_X, > CLIENT_TILING_Y, > + CLIENT_TILING_4, > CLIENT_NUM_TILING_TYPES > }; > > @@ -45,6 +107,36 @@ struct tiled_blits { > u32 height; > }; > > +static bool supports_x_tiling(const struct drm_i915_private *i915) > +{ > + int gen = GRAPHICS_VER(i915); > + > + if (gen < 12) > + return true; > + > + if (!HAS_LMEM(i915) || IS_DG1(i915)) > + return false; > + > + return true; > +} > + > +static bool fast_blit_ok(const struct blit_buffer *buf) > +{ > + int gen = GRAPHICS_VER(buf->vma->vm->i915); > + > + if (gen < 9) > + return false; > + > + if (gen < 12) > + return true; > + > + /* filter out platforms with unsupported X-tile support in fastblit */ > + if (buf->tiling == CLIENT_TILING_X && !supports_x_tiling(buf->vma->vm->i915)) > + return false; > + > + return true; > +} > + > static int prepare_blit(const struct tiled_blits *t, > struct blit_buffer *dst, > struct blit_buffer *src, > @@ -59,51 +151,103 @@ static int prepare_blit(const struct tiled_blits *t, > if (IS_ERR(cs)) > return PTR_ERR(cs); > > - *cs++ = MI_LOAD_REGISTER_IMM(1); > - *cs++ = i915_mmio_reg_offset(BCS_SWCTRL); > - cmd = (BCS_SRC_Y | BCS_DST_Y) << 16; > - if (src->tiling == CLIENT_TILING_Y) > - cmd |= BCS_SRC_Y; > - if (dst->tiling == CLIENT_TILING_Y) > - cmd |= BCS_DST_Y; > - *cs++ = cmd; > - > - cmd = MI_FLUSH_DW; > - if (ver >= 8) > - cmd++; > - *cs++ = cmd; > - *cs++ = 0; > - *cs++ = 0; > - *cs++ = 0; > - > - cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2); > - if (ver >= 8) > - cmd += 2; > - > - src_pitch = t->width * 4; > - if (src->tiling) { > - cmd |= XY_SRC_COPY_BLT_SRC_TILED; > - src_pitch /= 4; > - } > + if (fast_blit_ok(dst) && fast_blit_ok(src)) { > + struct intel_gt *gt = t->ce->engine->gt; > + u32 src_tiles = 0, dst_tiles = 0; > + u32 src_4t = 0, dst_4t = 0; > + > + /* Need to program BLIT_CCTL if it is not done previously > + * before using XY_FAST_COPY_BLT > + */ > + *cs++ = MI_LOAD_REGISTER_IMM(1); > + *cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base)); > + *cs++ = (BLIT_CCTL_SRC_MOCS(gt->mocs.uc_index) | > + BLIT_CCTL_DST_MOCS(gt->mocs.uc_index)); > + > + src_pitch = t->width; /* in dwords */ > + if (src->tiling == CLIENT_TILING_4) { > + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR); > + src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4; > + } else if (src->tiling == CLIENT_TILING_Y) { > + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR); > + } else if (src->tiling == CLIENT_TILING_X) { > + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X); > + } else { > + src_pitch *= 4; /* in bytes */ > + } > > - dst_pitch = t->width * 4; > - if (dst->tiling) { > - cmd |= XY_SRC_COPY_BLT_DST_TILED; > - dst_pitch /= 4; > - } > + dst_pitch = t->width; /* in dwords */ > + if (dst->tiling == CLIENT_TILING_4) { > + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR); > + dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4; > + } else if (dst->tiling == CLIENT_TILING_Y) { > + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR); > + } else if (dst->tiling == CLIENT_TILING_X) { > + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X); > + } else { > + dst_pitch *= 4; /* in bytes */ > + } > > - *cs++ = cmd; > - *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch; > - *cs++ = 0; > - *cs++ = t->height << 16 | t->width; > - *cs++ = lower_32_bits(dst->vma->node.start); > - if (use_64b_reloc) > + *cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2) | > + src_tiles | dst_tiles; > + *cs++ = src_4t | dst_4t | BLT_DEPTH_32 | dst_pitch; > + *cs++ = 0; > + *cs++ = t->height << 16 | t->width; > + *cs++ = lower_32_bits(dst->vma->node.start); > *cs++ = upper_32_bits(dst->vma->node.start); > - *cs++ = 0; > - *cs++ = src_pitch; > - *cs++ = lower_32_bits(src->vma->node.start); > - if (use_64b_reloc) > + *cs++ = 0; > + *cs++ = src_pitch; > + *cs++ = lower_32_bits(src->vma->node.start); > *cs++ = upper_32_bits(src->vma->node.start); > + } else { > + if (ver >= 6) { > + *cs++ = MI_LOAD_REGISTER_IMM(1); > + *cs++ = i915_mmio_reg_offset(BCS_SWCTRL); > + cmd = (BCS_SRC_Y | BCS_DST_Y) << 16; > + if (src->tiling == CLIENT_TILING_Y) > + cmd |= BCS_SRC_Y; > + if (dst->tiling == CLIENT_TILING_Y) > + cmd |= BCS_DST_Y; > + *cs++ = cmd; > + > + cmd = MI_FLUSH_DW; > + if (ver >= 8) > + cmd++; > + *cs++ = cmd; > + *cs++ = 0; > + *cs++ = 0; > + *cs++ = 0; > + } > + > + cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2); > + if (ver >= 8) > + cmd += 2; > + > + src_pitch = t->width * 4; > + if (src->tiling) { > + cmd |= XY_SRC_COPY_BLT_SRC_TILED; > + src_pitch /= 4; > + } > + > + dst_pitch = t->width * 4; > + if (dst->tiling) { > + cmd |= XY_SRC_COPY_BLT_DST_TILED; > + dst_pitch /= 4; > + } > + > + *cs++ = cmd; > + *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch; > + *cs++ = 0; > + *cs++ = t->height << 16 | t->width; > + *cs++ = lower_32_bits(dst->vma->node.start); > + if (use_64b_reloc) > + *cs++ = upper_32_bits(dst->vma->node.start); > + *cs++ = 0; > + *cs++ = src_pitch; > + *cs++ = lower_32_bits(src->vma->node.start); > + if (use_64b_reloc) > + *cs++ = upper_32_bits(src->vma->node.start); > + } > > *cs++ = MI_BATCH_BUFFER_END; > > @@ -181,7 +325,13 @@ static int tiled_blits_create_buffers(struct tiled_blits *t, > > t->buffers[i].vma = vma; > t->buffers[i].tiling = > - i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng); > + i915_prandom_u32_max_state(CLIENT_NUM_TILING_TYPES, prng); > + > + /* Platforms support either TileY or Tile4, not both */ > + if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y) > + t->buffers[i].tiling = CLIENT_TILING_4; > + else if (!HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_4) > + t->buffers[i].tiling = CLIENT_TILING_Y; > } > > return 0; > @@ -206,7 +356,8 @@ static u64 swizzle_bit(unsigned int bit, u64 offset) > static u64 tiled_offset(const struct intel_gt *gt, > u64 v, > unsigned int stride, > - enum client_tiling tiling) > + enum client_tiling tiling, > + int x_pos, int y_pos) > { > unsigned int swizzle; > u64 x, y; > @@ -216,7 +367,12 @@ static u64 tiled_offset(const struct intel_gt *gt, > > y = div64_u64_rem(v, stride, &x); > > - if (tiling == CLIENT_TILING_X) { > + if (tiling == CLIENT_TILING_4) { > + v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32); > + > + /* no swizzling for f-tiling */ > + swizzle = I915_BIT_6_SWIZZLE_NONE; > + } else if (tiling == CLIENT_TILING_X) { > v = div64_u64_rem(y, 8, &y) * stride * 8; > v += y * 512; > v += div64_u64_rem(x, 512, &x) << 12; > @@ -259,6 +415,7 @@ static const char *repr_tiling(enum client_tiling tiling) > case CLIENT_TILING_LINEAR: return "linear"; > case CLIENT_TILING_X: return "X"; > case CLIENT_TILING_Y: return "Y"; > + case CLIENT_TILING_4: return "F"; > default: return "unknown"; > } > } > @@ -284,7 +441,7 @@ static int verify_buffer(const struct tiled_blits *t, > } else { > u64 v = tiled_offset(buf->vma->vm->gt, > p * 4, t->width * 4, > - buf->tiling); > + buf->tiling, x, y); > > if (vaddr[v / sizeof(*vaddr)] != buf->start_val + p) > ret = -EINVAL; > @@ -504,6 +661,9 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng) > if (err) > return err; > > + /* Simulating GTT eviction of the same buffer / layout */ > + t->buffers[2].tiling = t->buffers[0].tiling; > + > /* Reposition so that we overlap the old addresses, and slightly off */ > err = tiled_blit(t, > &t->buffers[2], t->hole + t->align, > diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > index 556bca3be804..246ab8f7bf57 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > @@ -236,6 +236,28 @@ > #define XY_FAST_COLOR_BLT_DW 16 > #define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21) > #define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31 > + > +#define XY_FAST_COPY_BLT_D0_SRC_TILING_MASK REG_GENMASK(21, 20) > +#define XY_FAST_COPY_BLT_D0_DST_TILING_MASK REG_GENMASK(14, 13) > +#define XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode) \ > + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode) > +#define XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode) \ > + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode) > +#define LINEAR 0 > +#define TILE_X 0x1 > +#define XMAJOR 0x1 > +#define YMAJOR 0x2 > +#define TILE_64 0x3 > +#define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31) > +#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30) > +#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0) > +#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8) > +/* Note: MOCS value = (index << 1) */ > +#define BLIT_CCTL_SRC_MOCS(idx) \ > + REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (idx) << 1) > +#define BLIT_CCTL_DST_MOCS(idx) \ > + REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (idx) << 1) > + > #define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22) > #define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22) > #define XY_SRC_COPY_BLT_CMD (2 << 29 | 0x53 << 22) > -- > 2.35.1 >
On 5/13/2022 8:11 PM, Matt Roper wrote: > On Fri, May 13, 2022 at 10:47:54AM +0200, Nirmoy Das wrote: >> From: Bommu Krishnaiah <krishnaiah.bommu@intel.com> >> >> Enable Tile4 tiling mode on platform that supports >> Tile4 but no TileY like DG2. > Drive-by comment: the patch description doesn't match what the code is > actually doing. Tile4 is already enabled on these platforms (e.g., see > "drm/i915/dg2: Tile 4 plane format support"). This is meant to enable tile4 mode for selftest. I will update and resend. Thanks, Nirmoy > > This patch appears to just be updating selftest code, not enabling > anything new. > > > Matt > >> v3: add a function to find X-tile availability for a platform. >> v2: disable X-tile for iGPU in fastblit >> fix checkpath --strict warnings >> >> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com> >> Co-developed-by: Nirmoy Das <nirmoy.das@intel.com> >> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> >> --- >> .../i915/gem/selftests/i915_gem_client_blt.c | 250 ++++++++++++++---- >> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 ++ >> 2 files changed, 227 insertions(+), 45 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c >> index ddd0772fd828..3cfc621ef363 100644 >> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c >> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c >> @@ -6,6 +6,7 @@ >> #include "i915_selftest.h" >> >> #include "gt/intel_context.h" >> +#include "gt/intel_engine_regs.h" >> #include "gt/intel_engine_user.h" >> #include "gt/intel_gpu_commands.h" >> #include "gt/intel_gt.h" >> @@ -18,10 +19,71 @@ >> #include "huge_gem_object.h" >> #include "mock_context.h" >> >> +#define OW_SIZE 16 /* in bytes */ >> +#define F_SUBTILE_SIZE 64 /* in bytes */ >> +#define F_TILE_WIDTH 128 /* in bytes */ >> +#define F_TILE_HEIGHT 32 /* in pixels */ >> +#define F_SUBTILE_WIDTH OW_SIZE /* in bytes */ >> +#define F_SUBTILE_HEIGHT 4 /* in pixels */ >> + >> +static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp) >> +{ >> + int tile_base; >> + int tile_x, tile_y; >> + int swizzle, subtile; >> + int pixel_size = bpp / 8; >> + int pos; >> + >> + /* >> + * Subtile remapping for F tile. Note that map[a]==b implies map[b]==a >> + * so we can use the same table to tile and until. >> + */ >> + static const u8 f_subtile_map[] = { >> + 0, 1, 2, 3, 8, 9, 10, 11, >> + 4, 5, 6, 7, 12, 13, 14, 15, >> + 16, 17, 18, 19, 24, 25, 26, 27, >> + 20, 21, 22, 23, 28, 29, 30, 31, >> + 32, 33, 34, 35, 40, 41, 42, 43, >> + 36, 37, 38, 39, 44, 45, 46, 47, >> + 48, 49, 50, 51, 56, 57, 58, 59, >> + 52, 53, 54, 55, 60, 61, 62, 63 >> + }; >> + >> + x *= pixel_size; >> + /* >> + * Where does the 4k tile start (in bytes)? This is the same for Y and >> + * F so we can use the Y-tile algorithm to get to that point. >> + */ >> + tile_base = >> + y / F_TILE_HEIGHT * stride * F_TILE_HEIGHT + >> + x / F_TILE_WIDTH * 4096; >> + >> + /* Find pixel within tile */ >> + tile_x = x % F_TILE_WIDTH; >> + tile_y = y % F_TILE_HEIGHT; >> + >> + /* And figure out the subtile within the 4k tile */ >> + subtile = tile_y / F_SUBTILE_HEIGHT * 8 + tile_x / F_SUBTILE_WIDTH; >> + >> + /* Swizzle the subtile number according to the bspec diagram */ >> + swizzle = f_subtile_map[subtile]; >> + >> + /* Calculate new position */ >> + pos = tile_base + >> + swizzle * F_SUBTILE_SIZE + >> + tile_y % F_SUBTILE_HEIGHT * OW_SIZE + >> + tile_x % F_SUBTILE_WIDTH; >> + >> + GEM_BUG_ON(!IS_ALIGNED(pos, pixel_size)); >> + >> + return pos / pixel_size * 4; >> +} >> + >> enum client_tiling { >> CLIENT_TILING_LINEAR, >> CLIENT_TILING_X, >> CLIENT_TILING_Y, >> + CLIENT_TILING_4, >> CLIENT_NUM_TILING_TYPES >> }; >> >> @@ -45,6 +107,36 @@ struct tiled_blits { >> u32 height; >> }; >> >> +static bool supports_x_tiling(const struct drm_i915_private *i915) >> +{ >> + int gen = GRAPHICS_VER(i915); >> + >> + if (gen < 12) >> + return true; >> + >> + if (!HAS_LMEM(i915) || IS_DG1(i915)) >> + return false; >> + >> + return true; >> +} >> + >> +static bool fast_blit_ok(const struct blit_buffer *buf) >> +{ >> + int gen = GRAPHICS_VER(buf->vma->vm->i915); >> + >> + if (gen < 9) >> + return false; >> + >> + if (gen < 12) >> + return true; >> + >> + /* filter out platforms with unsupported X-tile support in fastblit */ >> + if (buf->tiling == CLIENT_TILING_X && !supports_x_tiling(buf->vma->vm->i915)) >> + return false; >> + >> + return true; >> +} >> + >> static int prepare_blit(const struct tiled_blits *t, >> struct blit_buffer *dst, >> struct blit_buffer *src, >> @@ -59,51 +151,103 @@ static int prepare_blit(const struct tiled_blits *t, >> if (IS_ERR(cs)) >> return PTR_ERR(cs); >> >> - *cs++ = MI_LOAD_REGISTER_IMM(1); >> - *cs++ = i915_mmio_reg_offset(BCS_SWCTRL); >> - cmd = (BCS_SRC_Y | BCS_DST_Y) << 16; >> - if (src->tiling == CLIENT_TILING_Y) >> - cmd |= BCS_SRC_Y; >> - if (dst->tiling == CLIENT_TILING_Y) >> - cmd |= BCS_DST_Y; >> - *cs++ = cmd; >> - >> - cmd = MI_FLUSH_DW; >> - if (ver >= 8) >> - cmd++; >> - *cs++ = cmd; >> - *cs++ = 0; >> - *cs++ = 0; >> - *cs++ = 0; >> - >> - cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2); >> - if (ver >= 8) >> - cmd += 2; >> - >> - src_pitch = t->width * 4; >> - if (src->tiling) { >> - cmd |= XY_SRC_COPY_BLT_SRC_TILED; >> - src_pitch /= 4; >> - } >> + if (fast_blit_ok(dst) && fast_blit_ok(src)) { >> + struct intel_gt *gt = t->ce->engine->gt; >> + u32 src_tiles = 0, dst_tiles = 0; >> + u32 src_4t = 0, dst_4t = 0; >> + >> + /* Need to program BLIT_CCTL if it is not done previously >> + * before using XY_FAST_COPY_BLT >> + */ >> + *cs++ = MI_LOAD_REGISTER_IMM(1); >> + *cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base)); >> + *cs++ = (BLIT_CCTL_SRC_MOCS(gt->mocs.uc_index) | >> + BLIT_CCTL_DST_MOCS(gt->mocs.uc_index)); >> + >> + src_pitch = t->width; /* in dwords */ >> + if (src->tiling == CLIENT_TILING_4) { >> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR); >> + src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4; >> + } else if (src->tiling == CLIENT_TILING_Y) { >> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR); >> + } else if (src->tiling == CLIENT_TILING_X) { >> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X); >> + } else { >> + src_pitch *= 4; /* in bytes */ >> + } >> >> - dst_pitch = t->width * 4; >> - if (dst->tiling) { >> - cmd |= XY_SRC_COPY_BLT_DST_TILED; >> - dst_pitch /= 4; >> - } >> + dst_pitch = t->width; /* in dwords */ >> + if (dst->tiling == CLIENT_TILING_4) { >> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR); >> + dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4; >> + } else if (dst->tiling == CLIENT_TILING_Y) { >> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR); >> + } else if (dst->tiling == CLIENT_TILING_X) { >> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X); >> + } else { >> + dst_pitch *= 4; /* in bytes */ >> + } >> >> - *cs++ = cmd; >> - *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch; >> - *cs++ = 0; >> - *cs++ = t->height << 16 | t->width; >> - *cs++ = lower_32_bits(dst->vma->node.start); >> - if (use_64b_reloc) >> + *cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2) | >> + src_tiles | dst_tiles; >> + *cs++ = src_4t | dst_4t | BLT_DEPTH_32 | dst_pitch; >> + *cs++ = 0; >> + *cs++ = t->height << 16 | t->width; >> + *cs++ = lower_32_bits(dst->vma->node.start); >> *cs++ = upper_32_bits(dst->vma->node.start); >> - *cs++ = 0; >> - *cs++ = src_pitch; >> - *cs++ = lower_32_bits(src->vma->node.start); >> - if (use_64b_reloc) >> + *cs++ = 0; >> + *cs++ = src_pitch; >> + *cs++ = lower_32_bits(src->vma->node.start); >> *cs++ = upper_32_bits(src->vma->node.start); >> + } else { >> + if (ver >= 6) { >> + *cs++ = MI_LOAD_REGISTER_IMM(1); >> + *cs++ = i915_mmio_reg_offset(BCS_SWCTRL); >> + cmd = (BCS_SRC_Y | BCS_DST_Y) << 16; >> + if (src->tiling == CLIENT_TILING_Y) >> + cmd |= BCS_SRC_Y; >> + if (dst->tiling == CLIENT_TILING_Y) >> + cmd |= BCS_DST_Y; >> + *cs++ = cmd; >> + >> + cmd = MI_FLUSH_DW; >> + if (ver >= 8) >> + cmd++; >> + *cs++ = cmd; >> + *cs++ = 0; >> + *cs++ = 0; >> + *cs++ = 0; >> + } >> + >> + cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2); >> + if (ver >= 8) >> + cmd += 2; >> + >> + src_pitch = t->width * 4; >> + if (src->tiling) { >> + cmd |= XY_SRC_COPY_BLT_SRC_TILED; >> + src_pitch /= 4; >> + } >> + >> + dst_pitch = t->width * 4; >> + if (dst->tiling) { >> + cmd |= XY_SRC_COPY_BLT_DST_TILED; >> + dst_pitch /= 4; >> + } >> + >> + *cs++ = cmd; >> + *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch; >> + *cs++ = 0; >> + *cs++ = t->height << 16 | t->width; >> + *cs++ = lower_32_bits(dst->vma->node.start); >> + if (use_64b_reloc) >> + *cs++ = upper_32_bits(dst->vma->node.start); >> + *cs++ = 0; >> + *cs++ = src_pitch; >> + *cs++ = lower_32_bits(src->vma->node.start); >> + if (use_64b_reloc) >> + *cs++ = upper_32_bits(src->vma->node.start); >> + } >> >> *cs++ = MI_BATCH_BUFFER_END; >> >> @@ -181,7 +325,13 @@ static int tiled_blits_create_buffers(struct tiled_blits *t, >> >> t->buffers[i].vma = vma; >> t->buffers[i].tiling = >> - i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng); >> + i915_prandom_u32_max_state(CLIENT_NUM_TILING_TYPES, prng); >> + >> + /* Platforms support either TileY or Tile4, not both */ >> + if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y) >> + t->buffers[i].tiling = CLIENT_TILING_4; >> + else if (!HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_4) >> + t->buffers[i].tiling = CLIENT_TILING_Y; >> } >> >> return 0; >> @@ -206,7 +356,8 @@ static u64 swizzle_bit(unsigned int bit, u64 offset) >> static u64 tiled_offset(const struct intel_gt *gt, >> u64 v, >> unsigned int stride, >> - enum client_tiling tiling) >> + enum client_tiling tiling, >> + int x_pos, int y_pos) >> { >> unsigned int swizzle; >> u64 x, y; >> @@ -216,7 +367,12 @@ static u64 tiled_offset(const struct intel_gt *gt, >> >> y = div64_u64_rem(v, stride, &x); >> >> - if (tiling == CLIENT_TILING_X) { >> + if (tiling == CLIENT_TILING_4) { >> + v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32); >> + >> + /* no swizzling for f-tiling */ >> + swizzle = I915_BIT_6_SWIZZLE_NONE; >> + } else if (tiling == CLIENT_TILING_X) { >> v = div64_u64_rem(y, 8, &y) * stride * 8; >> v += y * 512; >> v += div64_u64_rem(x, 512, &x) << 12; >> @@ -259,6 +415,7 @@ static const char *repr_tiling(enum client_tiling tiling) >> case CLIENT_TILING_LINEAR: return "linear"; >> case CLIENT_TILING_X: return "X"; >> case CLIENT_TILING_Y: return "Y"; >> + case CLIENT_TILING_4: return "F"; >> default: return "unknown"; >> } >> } >> @@ -284,7 +441,7 @@ static int verify_buffer(const struct tiled_blits *t, >> } else { >> u64 v = tiled_offset(buf->vma->vm->gt, >> p * 4, t->width * 4, >> - buf->tiling); >> + buf->tiling, x, y); >> >> if (vaddr[v / sizeof(*vaddr)] != buf->start_val + p) >> ret = -EINVAL; >> @@ -504,6 +661,9 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng) >> if (err) >> return err; >> >> + /* Simulating GTT eviction of the same buffer / layout */ >> + t->buffers[2].tiling = t->buffers[0].tiling; >> + >> /* Reposition so that we overlap the old addresses, and slightly off */ >> err = tiled_blit(t, >> &t->buffers[2], t->hole + t->align, >> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h >> index 556bca3be804..246ab8f7bf57 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h >> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h >> @@ -236,6 +236,28 @@ >> #define XY_FAST_COLOR_BLT_DW 16 >> #define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21) >> #define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31 >> + >> +#define XY_FAST_COPY_BLT_D0_SRC_TILING_MASK REG_GENMASK(21, 20) >> +#define XY_FAST_COPY_BLT_D0_DST_TILING_MASK REG_GENMASK(14, 13) >> +#define XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode) \ >> + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode) >> +#define XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode) \ >> + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode) >> +#define LINEAR 0 >> +#define TILE_X 0x1 >> +#define XMAJOR 0x1 >> +#define YMAJOR 0x2 >> +#define TILE_64 0x3 >> +#define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31) >> +#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30) >> +#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0) >> +#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8) >> +/* Note: MOCS value = (index << 1) */ >> +#define BLIT_CCTL_SRC_MOCS(idx) \ >> + REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (idx) << 1) >> +#define BLIT_CCTL_DST_MOCS(idx) \ >> + REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (idx) << 1) >> + >> #define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22) >> #define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22) >> #define XY_SRC_COPY_BLT_CMD (2 << 29 | 0x53 << 22) >> -- >> 2.35.1 >>
On Fri, May 13, 2022 at 10:47:54AM +0200, Nirmoy Das wrote: > From: Bommu Krishnaiah <krishnaiah.bommu@intel.com> > > Enable Tile4 tiling mode on platform that supports > Tile4 but no TileY like DG2. > > v3: add a function to find X-tile availability for a platform. > v2: disable X-tile for iGPU in fastblit > fix checkpath --strict warnings > > Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com> > Co-developed-by: Nirmoy Das <nirmoy.das@intel.com> > Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> Looks good for me, X is skipped on DG1 and integrated (gen12): Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com> -- Zbigniew > --- > .../i915/gem/selftests/i915_gem_client_blt.c | 250 ++++++++++++++---- > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 ++ > 2 files changed, 227 insertions(+), 45 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c > index ddd0772fd828..3cfc621ef363 100644 > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c > @@ -6,6 +6,7 @@ > #include "i915_selftest.h" > > #include "gt/intel_context.h" > +#include "gt/intel_engine_regs.h" > #include "gt/intel_engine_user.h" > #include "gt/intel_gpu_commands.h" > #include "gt/intel_gt.h" > @@ -18,10 +19,71 @@ > #include "huge_gem_object.h" > #include "mock_context.h" > > +#define OW_SIZE 16 /* in bytes */ > +#define F_SUBTILE_SIZE 64 /* in bytes */ > +#define F_TILE_WIDTH 128 /* in bytes */ > +#define F_TILE_HEIGHT 32 /* in pixels */ > +#define F_SUBTILE_WIDTH OW_SIZE /* in bytes */ > +#define F_SUBTILE_HEIGHT 4 /* in pixels */ > + > +static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp) > +{ > + int tile_base; > + int tile_x, tile_y; > + int swizzle, subtile; > + int pixel_size = bpp / 8; > + int pos; > + > + /* > + * Subtile remapping for F tile. Note that map[a]==b implies map[b]==a > + * so we can use the same table to tile and until. > + */ > + static const u8 f_subtile_map[] = { > + 0, 1, 2, 3, 8, 9, 10, 11, > + 4, 5, 6, 7, 12, 13, 14, 15, > + 16, 17, 18, 19, 24, 25, 26, 27, > + 20, 21, 22, 23, 28, 29, 30, 31, > + 32, 33, 34, 35, 40, 41, 42, 43, > + 36, 37, 38, 39, 44, 45, 46, 47, > + 48, 49, 50, 51, 56, 57, 58, 59, > + 52, 53, 54, 55, 60, 61, 62, 63 > + }; > + > + x *= pixel_size; > + /* > + * Where does the 4k tile start (in bytes)? This is the same for Y and > + * F so we can use the Y-tile algorithm to get to that point. > + */ > + tile_base = > + y / F_TILE_HEIGHT * stride * F_TILE_HEIGHT + > + x / F_TILE_WIDTH * 4096; > + > + /* Find pixel within tile */ > + tile_x = x % F_TILE_WIDTH; > + tile_y = y % F_TILE_HEIGHT; > + > + /* And figure out the subtile within the 4k tile */ > + subtile = tile_y / F_SUBTILE_HEIGHT * 8 + tile_x / F_SUBTILE_WIDTH; > + > + /* Swizzle the subtile number according to the bspec diagram */ > + swizzle = f_subtile_map[subtile]; > + > + /* Calculate new position */ > + pos = tile_base + > + swizzle * F_SUBTILE_SIZE + > + tile_y % F_SUBTILE_HEIGHT * OW_SIZE + > + tile_x % F_SUBTILE_WIDTH; > + > + GEM_BUG_ON(!IS_ALIGNED(pos, pixel_size)); > + > + return pos / pixel_size * 4; > +} > + > enum client_tiling { > CLIENT_TILING_LINEAR, > CLIENT_TILING_X, > CLIENT_TILING_Y, > + CLIENT_TILING_4, > CLIENT_NUM_TILING_TYPES > }; > > @@ -45,6 +107,36 @@ struct tiled_blits { > u32 height; > }; > > +static bool supports_x_tiling(const struct drm_i915_private *i915) > +{ > + int gen = GRAPHICS_VER(i915); > + > + if (gen < 12) > + return true; > + > + if (!HAS_LMEM(i915) || IS_DG1(i915)) > + return false; > + > + return true; > +} > + > +static bool fast_blit_ok(const struct blit_buffer *buf) > +{ > + int gen = GRAPHICS_VER(buf->vma->vm->i915); > + > + if (gen < 9) > + return false; > + > + if (gen < 12) > + return true; > + > + /* filter out platforms with unsupported X-tile support in fastblit */ > + if (buf->tiling == CLIENT_TILING_X && !supports_x_tiling(buf->vma->vm->i915)) > + return false; > + > + return true; > +} > + > static int prepare_blit(const struct tiled_blits *t, > struct blit_buffer *dst, > struct blit_buffer *src, > @@ -59,51 +151,103 @@ static int prepare_blit(const struct tiled_blits *t, > if (IS_ERR(cs)) > return PTR_ERR(cs); > > - *cs++ = MI_LOAD_REGISTER_IMM(1); > - *cs++ = i915_mmio_reg_offset(BCS_SWCTRL); > - cmd = (BCS_SRC_Y | BCS_DST_Y) << 16; > - if (src->tiling == CLIENT_TILING_Y) > - cmd |= BCS_SRC_Y; > - if (dst->tiling == CLIENT_TILING_Y) > - cmd |= BCS_DST_Y; > - *cs++ = cmd; > - > - cmd = MI_FLUSH_DW; > - if (ver >= 8) > - cmd++; > - *cs++ = cmd; > - *cs++ = 0; > - *cs++ = 0; > - *cs++ = 0; > - > - cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2); > - if (ver >= 8) > - cmd += 2; > - > - src_pitch = t->width * 4; > - if (src->tiling) { > - cmd |= XY_SRC_COPY_BLT_SRC_TILED; > - src_pitch /= 4; > - } > + if (fast_blit_ok(dst) && fast_blit_ok(src)) { > + struct intel_gt *gt = t->ce->engine->gt; > + u32 src_tiles = 0, dst_tiles = 0; > + u32 src_4t = 0, dst_4t = 0; > + > + /* Need to program BLIT_CCTL if it is not done previously > + * before using XY_FAST_COPY_BLT > + */ > + *cs++ = MI_LOAD_REGISTER_IMM(1); > + *cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base)); > + *cs++ = (BLIT_CCTL_SRC_MOCS(gt->mocs.uc_index) | > + BLIT_CCTL_DST_MOCS(gt->mocs.uc_index)); > + > + src_pitch = t->width; /* in dwords */ > + if (src->tiling == CLIENT_TILING_4) { > + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR); > + src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4; > + } else if (src->tiling == CLIENT_TILING_Y) { > + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR); > + } else if (src->tiling == CLIENT_TILING_X) { > + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X); > + } else { > + src_pitch *= 4; /* in bytes */ > + } > > - dst_pitch = t->width * 4; > - if (dst->tiling) { > - cmd |= XY_SRC_COPY_BLT_DST_TILED; > - dst_pitch /= 4; > - } > + dst_pitch = t->width; /* in dwords */ > + if (dst->tiling == CLIENT_TILING_4) { > + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR); > + dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4; > + } else if (dst->tiling == CLIENT_TILING_Y) { > + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR); > + } else if (dst->tiling == CLIENT_TILING_X) { > + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X); > + } else { > + dst_pitch *= 4; /* in bytes */ > + } > > - *cs++ = cmd; > - *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch; > - *cs++ = 0; > - *cs++ = t->height << 16 | t->width; > - *cs++ = lower_32_bits(dst->vma->node.start); > - if (use_64b_reloc) > + *cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2) | > + src_tiles | dst_tiles; > + *cs++ = src_4t | dst_4t | BLT_DEPTH_32 | dst_pitch; > + *cs++ = 0; > + *cs++ = t->height << 16 | t->width; > + *cs++ = lower_32_bits(dst->vma->node.start); > *cs++ = upper_32_bits(dst->vma->node.start); > - *cs++ = 0; > - *cs++ = src_pitch; > - *cs++ = lower_32_bits(src->vma->node.start); > - if (use_64b_reloc) > + *cs++ = 0; > + *cs++ = src_pitch; > + *cs++ = lower_32_bits(src->vma->node.start); > *cs++ = upper_32_bits(src->vma->node.start); > + } else { > + if (ver >= 6) { > + *cs++ = MI_LOAD_REGISTER_IMM(1); > + *cs++ = i915_mmio_reg_offset(BCS_SWCTRL); > + cmd = (BCS_SRC_Y | BCS_DST_Y) << 16; > + if (src->tiling == CLIENT_TILING_Y) > + cmd |= BCS_SRC_Y; > + if (dst->tiling == CLIENT_TILING_Y) > + cmd |= BCS_DST_Y; > + *cs++ = cmd; > + > + cmd = MI_FLUSH_DW; > + if (ver >= 8) > + cmd++; > + *cs++ = cmd; > + *cs++ = 0; > + *cs++ = 0; > + *cs++ = 0; > + } > + > + cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2); > + if (ver >= 8) > + cmd += 2; > + > + src_pitch = t->width * 4; > + if (src->tiling) { > + cmd |= XY_SRC_COPY_BLT_SRC_TILED; > + src_pitch /= 4; > + } > + > + dst_pitch = t->width * 4; > + if (dst->tiling) { > + cmd |= XY_SRC_COPY_BLT_DST_TILED; > + dst_pitch /= 4; > + } > + > + *cs++ = cmd; > + *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch; > + *cs++ = 0; > + *cs++ = t->height << 16 | t->width; > + *cs++ = lower_32_bits(dst->vma->node.start); > + if (use_64b_reloc) > + *cs++ = upper_32_bits(dst->vma->node.start); > + *cs++ = 0; > + *cs++ = src_pitch; > + *cs++ = lower_32_bits(src->vma->node.start); > + if (use_64b_reloc) > + *cs++ = upper_32_bits(src->vma->node.start); > + } > > *cs++ = MI_BATCH_BUFFER_END; > > @@ -181,7 +325,13 @@ static int tiled_blits_create_buffers(struct tiled_blits *t, > > t->buffers[i].vma = vma; > t->buffers[i].tiling = > - i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng); > + i915_prandom_u32_max_state(CLIENT_NUM_TILING_TYPES, prng); > + > + /* Platforms support either TileY or Tile4, not both */ > + if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y) > + t->buffers[i].tiling = CLIENT_TILING_4; > + else if (!HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_4) > + t->buffers[i].tiling = CLIENT_TILING_Y; > } > > return 0; > @@ -206,7 +356,8 @@ static u64 swizzle_bit(unsigned int bit, u64 offset) > static u64 tiled_offset(const struct intel_gt *gt, > u64 v, > unsigned int stride, > - enum client_tiling tiling) > + enum client_tiling tiling, > + int x_pos, int y_pos) > { > unsigned int swizzle; > u64 x, y; > @@ -216,7 +367,12 @@ static u64 tiled_offset(const struct intel_gt *gt, > > y = div64_u64_rem(v, stride, &x); > > - if (tiling == CLIENT_TILING_X) { > + if (tiling == CLIENT_TILING_4) { > + v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32); > + > + /* no swizzling for f-tiling */ > + swizzle = I915_BIT_6_SWIZZLE_NONE; > + } else if (tiling == CLIENT_TILING_X) { > v = div64_u64_rem(y, 8, &y) * stride * 8; > v += y * 512; > v += div64_u64_rem(x, 512, &x) << 12; > @@ -259,6 +415,7 @@ static const char *repr_tiling(enum client_tiling tiling) > case CLIENT_TILING_LINEAR: return "linear"; > case CLIENT_TILING_X: return "X"; > case CLIENT_TILING_Y: return "Y"; > + case CLIENT_TILING_4: return "F"; > default: return "unknown"; > } > } > @@ -284,7 +441,7 @@ static int verify_buffer(const struct tiled_blits *t, > } else { > u64 v = tiled_offset(buf->vma->vm->gt, > p * 4, t->width * 4, > - buf->tiling); > + buf->tiling, x, y); > > if (vaddr[v / sizeof(*vaddr)] != buf->start_val + p) > ret = -EINVAL; > @@ -504,6 +661,9 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng) > if (err) > return err; > > + /* Simulating GTT eviction of the same buffer / layout */ > + t->buffers[2].tiling = t->buffers[0].tiling; > + > /* Reposition so that we overlap the old addresses, and slightly off */ > err = tiled_blit(t, > &t->buffers[2], t->hole + t->align, > diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > index 556bca3be804..246ab8f7bf57 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > @@ -236,6 +236,28 @@ > #define XY_FAST_COLOR_BLT_DW 16 > #define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21) > #define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31 > + > +#define XY_FAST_COPY_BLT_D0_SRC_TILING_MASK REG_GENMASK(21, 20) > +#define XY_FAST_COPY_BLT_D0_DST_TILING_MASK REG_GENMASK(14, 13) > +#define XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode) \ > + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode) > +#define XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode) \ > + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode) > +#define LINEAR 0 > +#define TILE_X 0x1 > +#define XMAJOR 0x1 > +#define YMAJOR 0x2 > +#define TILE_64 0x3 > +#define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31) > +#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30) > +#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0) > +#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8) > +/* Note: MOCS value = (index << 1) */ > +#define BLIT_CCTL_SRC_MOCS(idx) \ > + REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (idx) << 1) > +#define BLIT_CCTL_DST_MOCS(idx) \ > + REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (idx) << 1) > + > #define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22) > #define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22) > #define XY_SRC_COPY_BLT_CMD (2 << 29 | 0x53 << 22) > -- > 2.35.1 >
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c index ddd0772fd828..3cfc621ef363 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c @@ -6,6 +6,7 @@ #include "i915_selftest.h" #include "gt/intel_context.h" +#include "gt/intel_engine_regs.h" #include "gt/intel_engine_user.h" #include "gt/intel_gpu_commands.h" #include "gt/intel_gt.h" @@ -18,10 +19,71 @@ #include "huge_gem_object.h" #include "mock_context.h" +#define OW_SIZE 16 /* in bytes */ +#define F_SUBTILE_SIZE 64 /* in bytes */ +#define F_TILE_WIDTH 128 /* in bytes */ +#define F_TILE_HEIGHT 32 /* in pixels */ +#define F_SUBTILE_WIDTH OW_SIZE /* in bytes */ +#define F_SUBTILE_HEIGHT 4 /* in pixels */ + +static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp) +{ + int tile_base; + int tile_x, tile_y; + int swizzle, subtile; + int pixel_size = bpp / 8; + int pos; + + /* + * Subtile remapping for F tile. Note that map[a]==b implies map[b]==a + * so we can use the same table to tile and until. + */ + static const u8 f_subtile_map[] = { + 0, 1, 2, 3, 8, 9, 10, 11, + 4, 5, 6, 7, 12, 13, 14, 15, + 16, 17, 18, 19, 24, 25, 26, 27, + 20, 21, 22, 23, 28, 29, 30, 31, + 32, 33, 34, 35, 40, 41, 42, 43, + 36, 37, 38, 39, 44, 45, 46, 47, + 48, 49, 50, 51, 56, 57, 58, 59, + 52, 53, 54, 55, 60, 61, 62, 63 + }; + + x *= pixel_size; + /* + * Where does the 4k tile start (in bytes)? This is the same for Y and + * F so we can use the Y-tile algorithm to get to that point. + */ + tile_base = + y / F_TILE_HEIGHT * stride * F_TILE_HEIGHT + + x / F_TILE_WIDTH * 4096; + + /* Find pixel within tile */ + tile_x = x % F_TILE_WIDTH; + tile_y = y % F_TILE_HEIGHT; + + /* And figure out the subtile within the 4k tile */ + subtile = tile_y / F_SUBTILE_HEIGHT * 8 + tile_x / F_SUBTILE_WIDTH; + + /* Swizzle the subtile number according to the bspec diagram */ + swizzle = f_subtile_map[subtile]; + + /* Calculate new position */ + pos = tile_base + + swizzle * F_SUBTILE_SIZE + + tile_y % F_SUBTILE_HEIGHT * OW_SIZE + + tile_x % F_SUBTILE_WIDTH; + + GEM_BUG_ON(!IS_ALIGNED(pos, pixel_size)); + + return pos / pixel_size * 4; +} + enum client_tiling { CLIENT_TILING_LINEAR, CLIENT_TILING_X, CLIENT_TILING_Y, + CLIENT_TILING_4, CLIENT_NUM_TILING_TYPES }; @@ -45,6 +107,36 @@ struct tiled_blits { u32 height; }; +static bool supports_x_tiling(const struct drm_i915_private *i915) +{ + int gen = GRAPHICS_VER(i915); + + if (gen < 12) + return true; + + if (!HAS_LMEM(i915) || IS_DG1(i915)) + return false; + + return true; +} + +static bool fast_blit_ok(const struct blit_buffer *buf) +{ + int gen = GRAPHICS_VER(buf->vma->vm->i915); + + if (gen < 9) + return false; + + if (gen < 12) + return true; + + /* filter out platforms with unsupported X-tile support in fastblit */ + if (buf->tiling == CLIENT_TILING_X && !supports_x_tiling(buf->vma->vm->i915)) + return false; + + return true; +} + static int prepare_blit(const struct tiled_blits *t, struct blit_buffer *dst, struct blit_buffer *src, @@ -59,51 +151,103 @@ static int prepare_blit(const struct tiled_blits *t, if (IS_ERR(cs)) return PTR_ERR(cs); - *cs++ = MI_LOAD_REGISTER_IMM(1); - *cs++ = i915_mmio_reg_offset(BCS_SWCTRL); - cmd = (BCS_SRC_Y | BCS_DST_Y) << 16; - if (src->tiling == CLIENT_TILING_Y) - cmd |= BCS_SRC_Y; - if (dst->tiling == CLIENT_TILING_Y) - cmd |= BCS_DST_Y; - *cs++ = cmd; - - cmd = MI_FLUSH_DW; - if (ver >= 8) - cmd++; - *cs++ = cmd; - *cs++ = 0; - *cs++ = 0; - *cs++ = 0; - - cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2); - if (ver >= 8) - cmd += 2; - - src_pitch = t->width * 4; - if (src->tiling) { - cmd |= XY_SRC_COPY_BLT_SRC_TILED; - src_pitch /= 4; - } + if (fast_blit_ok(dst) && fast_blit_ok(src)) { + struct intel_gt *gt = t->ce->engine->gt; + u32 src_tiles = 0, dst_tiles = 0; + u32 src_4t = 0, dst_4t = 0; + + /* Need to program BLIT_CCTL if it is not done previously + * before using XY_FAST_COPY_BLT + */ + *cs++ = MI_LOAD_REGISTER_IMM(1); + *cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base)); + *cs++ = (BLIT_CCTL_SRC_MOCS(gt->mocs.uc_index) | + BLIT_CCTL_DST_MOCS(gt->mocs.uc_index)); + + src_pitch = t->width; /* in dwords */ + if (src->tiling == CLIENT_TILING_4) { + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR); + src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4; + } else if (src->tiling == CLIENT_TILING_Y) { + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR); + } else if (src->tiling == CLIENT_TILING_X) { + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X); + } else { + src_pitch *= 4; /* in bytes */ + } - dst_pitch = t->width * 4; - if (dst->tiling) { - cmd |= XY_SRC_COPY_BLT_DST_TILED; - dst_pitch /= 4; - } + dst_pitch = t->width; /* in dwords */ + if (dst->tiling == CLIENT_TILING_4) { + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR); + dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4; + } else if (dst->tiling == CLIENT_TILING_Y) { + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR); + } else if (dst->tiling == CLIENT_TILING_X) { + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X); + } else { + dst_pitch *= 4; /* in bytes */ + } - *cs++ = cmd; - *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch; - *cs++ = 0; - *cs++ = t->height << 16 | t->width; - *cs++ = lower_32_bits(dst->vma->node.start); - if (use_64b_reloc) + *cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2) | + src_tiles | dst_tiles; + *cs++ = src_4t | dst_4t | BLT_DEPTH_32 | dst_pitch; + *cs++ = 0; + *cs++ = t->height << 16 | t->width; + *cs++ = lower_32_bits(dst->vma->node.start); *cs++ = upper_32_bits(dst->vma->node.start); - *cs++ = 0; - *cs++ = src_pitch; - *cs++ = lower_32_bits(src->vma->node.start); - if (use_64b_reloc) + *cs++ = 0; + *cs++ = src_pitch; + *cs++ = lower_32_bits(src->vma->node.start); *cs++ = upper_32_bits(src->vma->node.start); + } else { + if (ver >= 6) { + *cs++ = MI_LOAD_REGISTER_IMM(1); + *cs++ = i915_mmio_reg_offset(BCS_SWCTRL); + cmd = (BCS_SRC_Y | BCS_DST_Y) << 16; + if (src->tiling == CLIENT_TILING_Y) + cmd |= BCS_SRC_Y; + if (dst->tiling == CLIENT_TILING_Y) + cmd |= BCS_DST_Y; + *cs++ = cmd; + + cmd = MI_FLUSH_DW; + if (ver >= 8) + cmd++; + *cs++ = cmd; + *cs++ = 0; + *cs++ = 0; + *cs++ = 0; + } + + cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2); + if (ver >= 8) + cmd += 2; + + src_pitch = t->width * 4; + if (src->tiling) { + cmd |= XY_SRC_COPY_BLT_SRC_TILED; + src_pitch /= 4; + } + + dst_pitch = t->width * 4; + if (dst->tiling) { + cmd |= XY_SRC_COPY_BLT_DST_TILED; + dst_pitch /= 4; + } + + *cs++ = cmd; + *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch; + *cs++ = 0; + *cs++ = t->height << 16 | t->width; + *cs++ = lower_32_bits(dst->vma->node.start); + if (use_64b_reloc) + *cs++ = upper_32_bits(dst->vma->node.start); + *cs++ = 0; + *cs++ = src_pitch; + *cs++ = lower_32_bits(src->vma->node.start); + if (use_64b_reloc) + *cs++ = upper_32_bits(src->vma->node.start); + } *cs++ = MI_BATCH_BUFFER_END; @@ -181,7 +325,13 @@ static int tiled_blits_create_buffers(struct tiled_blits *t, t->buffers[i].vma = vma; t->buffers[i].tiling = - i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng); + i915_prandom_u32_max_state(CLIENT_NUM_TILING_TYPES, prng); + + /* Platforms support either TileY or Tile4, not both */ + if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y) + t->buffers[i].tiling = CLIENT_TILING_4; + else if (!HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_4) + t->buffers[i].tiling = CLIENT_TILING_Y; } return 0; @@ -206,7 +356,8 @@ static u64 swizzle_bit(unsigned int bit, u64 offset) static u64 tiled_offset(const struct intel_gt *gt, u64 v, unsigned int stride, - enum client_tiling tiling) + enum client_tiling tiling, + int x_pos, int y_pos) { unsigned int swizzle; u64 x, y; @@ -216,7 +367,12 @@ static u64 tiled_offset(const struct intel_gt *gt, y = div64_u64_rem(v, stride, &x); - if (tiling == CLIENT_TILING_X) { + if (tiling == CLIENT_TILING_4) { + v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32); + + /* no swizzling for f-tiling */ + swizzle = I915_BIT_6_SWIZZLE_NONE; + } else if (tiling == CLIENT_TILING_X) { v = div64_u64_rem(y, 8, &y) * stride * 8; v += y * 512; v += div64_u64_rem(x, 512, &x) << 12; @@ -259,6 +415,7 @@ static const char *repr_tiling(enum client_tiling tiling) case CLIENT_TILING_LINEAR: return "linear"; case CLIENT_TILING_X: return "X"; case CLIENT_TILING_Y: return "Y"; + case CLIENT_TILING_4: return "F"; default: return "unknown"; } } @@ -284,7 +441,7 @@ static int verify_buffer(const struct tiled_blits *t, } else { u64 v = tiled_offset(buf->vma->vm->gt, p * 4, t->width * 4, - buf->tiling); + buf->tiling, x, y); if (vaddr[v / sizeof(*vaddr)] != buf->start_val + p) ret = -EINVAL; @@ -504,6 +661,9 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng) if (err) return err; + /* Simulating GTT eviction of the same buffer / layout */ + t->buffers[2].tiling = t->buffers[0].tiling; + /* Reposition so that we overlap the old addresses, and slightly off */ err = tiled_blit(t, &t->buffers[2], t->hole + t->align, diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h index 556bca3be804..246ab8f7bf57 100644 --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h @@ -236,6 +236,28 @@ #define XY_FAST_COLOR_BLT_DW 16 #define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21) #define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31 + +#define XY_FAST_COPY_BLT_D0_SRC_TILING_MASK REG_GENMASK(21, 20) +#define XY_FAST_COPY_BLT_D0_DST_TILING_MASK REG_GENMASK(14, 13) +#define XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode) \ + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode) +#define XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode) \ + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode) +#define LINEAR 0 +#define TILE_X 0x1 +#define XMAJOR 0x1 +#define YMAJOR 0x2 +#define TILE_64 0x3 +#define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31) +#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30) +#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0) +#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8) +/* Note: MOCS value = (index << 1) */ +#define BLIT_CCTL_SRC_MOCS(idx) \ + REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (idx) << 1) +#define BLIT_CCTL_DST_MOCS(idx) \ + REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (idx) << 1) + #define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22) #define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22) #define XY_SRC_COPY_BLT_CMD (2 << 29 | 0x53 << 22)