| Message ID | 20220516033357.12371-1-liweiwei@iscas.ac.cn (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize | expand |
On Mon, May 16, 2022 at 1:36 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > - setting ext_g will implicitly set ext_i > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > --- > slirp | 2 +- > target/riscv/cpu.c | 23 ++++++++++++----------- > 2 files changed, 13 insertions(+), 12 deletions(-) > > diff --git a/slirp b/slirp > index 9d59bb775d..a88d9ace23 160000 > --- a/slirp > +++ b/slirp > @@ -1 +1 @@ > -Subproject commit 9d59bb775d6294c8b447a88512f7bb43f12a25a8 > +Subproject commit a88d9ace234a24ce1c17189642ef9104799425e0 Looks like you accidentally included a submodule change Alistair > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index ccacdee215..b12f69c584 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -583,6 +583,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > if (env->misa_ext == 0) { > uint32_t ext = 0; > > + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & > + cpu->cfg.ext_a & cpu->cfg.ext_f & > + cpu->cfg.ext_d)) { > + warn_report("Setting G will also set IMAFD"); > + cpu->cfg.ext_i = true; > + cpu->cfg.ext_m = true; > + cpu->cfg.ext_a = true; > + cpu->cfg.ext_f = true; > + cpu->cfg.ext_d = true; > + } > + > + > /* Do some ISA extension error checking */ > if (cpu->cfg.ext_i && cpu->cfg.ext_e) { > error_setg(errp, > @@ -596,17 +608,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > return; > } > > - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & > - cpu->cfg.ext_a & cpu->cfg.ext_f & > - cpu->cfg.ext_d)) { > - warn_report("Setting G will also set IMAFD"); > - cpu->cfg.ext_i = true; > - cpu->cfg.ext_m = true; > - cpu->cfg.ext_a = true; > - cpu->cfg.ext_f = true; > - cpu->cfg.ext_d = true; > - } > - > if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || > cpu->cfg.ext_zhinxmin) { > cpu->cfg.ext_zfinx = true; > -- > 2.17.1 > >
在 2022/5/17 上午8:23, Alistair Francis 写道: > On Mon, May 16, 2022 at 1:36 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: >> - setting ext_g will implicitly set ext_i >> >> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> >> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> >> --- >> slirp | 2 +- >> target/riscv/cpu.c | 23 ++++++++++++----------- >> 2 files changed, 13 insertions(+), 12 deletions(-) >> >> diff --git a/slirp b/slirp >> index 9d59bb775d..a88d9ace23 160000 >> --- a/slirp >> +++ b/slirp >> @@ -1 +1 @@ >> -Subproject commit 9d59bb775d6294c8b447a88512f7bb43f12a25a8 >> +Subproject commit a88d9ace234a24ce1c17189642ef9104799425e0 > Looks like you accidentally included a submodule change > > Alistair Sorry. I'll fix this later. Regards, Weiwei Li >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index ccacdee215..b12f69c584 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -583,6 +583,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) >> if (env->misa_ext == 0) { >> uint32_t ext = 0; >> >> + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & >> + cpu->cfg.ext_a & cpu->cfg.ext_f & >> + cpu->cfg.ext_d)) { >> + warn_report("Setting G will also set IMAFD"); >> + cpu->cfg.ext_i = true; >> + cpu->cfg.ext_m = true; >> + cpu->cfg.ext_a = true; >> + cpu->cfg.ext_f = true; >> + cpu->cfg.ext_d = true; >> + } >> + >> + >> /* Do some ISA extension error checking */ >> if (cpu->cfg.ext_i && cpu->cfg.ext_e) { >> error_setg(errp, >> @@ -596,17 +608,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) >> return; >> } >> >> - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & >> - cpu->cfg.ext_a & cpu->cfg.ext_f & >> - cpu->cfg.ext_d)) { >> - warn_report("Setting G will also set IMAFD"); >> - cpu->cfg.ext_i = true; >> - cpu->cfg.ext_m = true; >> - cpu->cfg.ext_a = true; >> - cpu->cfg.ext_f = true; >> - cpu->cfg.ext_d = true; >> - } >> - >> if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || >> cpu->cfg.ext_zhinxmin) { >> cpu->cfg.ext_zfinx = true; >> -- >> 2.17.1 >> >>
diff --git a/slirp b/slirp index 9d59bb775d..a88d9ace23 160000 --- a/slirp +++ b/slirp @@ -1 +1 @@ -Subproject commit 9d59bb775d6294c8b447a88512f7bb43f12a25a8 +Subproject commit a88d9ace234a24ce1c17189642ef9104799425e0 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ccacdee215..b12f69c584 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -583,6 +583,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (env->misa_ext == 0) { uint32_t ext = 0; + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & + cpu->cfg.ext_a & cpu->cfg.ext_f & + cpu->cfg.ext_d)) { + warn_report("Setting G will also set IMAFD"); + cpu->cfg.ext_i = true; + cpu->cfg.ext_m = true; + cpu->cfg.ext_a = true; + cpu->cfg.ext_f = true; + cpu->cfg.ext_d = true; + } + + /* Do some ISA extension error checking */ if (cpu->cfg.ext_i && cpu->cfg.ext_e) { error_setg(errp, @@ -596,17 +608,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & - cpu->cfg.ext_a & cpu->cfg.ext_f & - cpu->cfg.ext_d)) { - warn_report("Setting G will also set IMAFD"); - cpu->cfg.ext_i = true; - cpu->cfg.ext_m = true; - cpu->cfg.ext_a = true; - cpu->cfg.ext_f = true; - cpu->cfg.ext_d = true; - } - if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || cpu->cfg.ext_zhinxmin) { cpu->cfg.ext_zfinx = true;