| Message ID | 20220519153107.696864-7-clement.leger@bootlin.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | add support for Renesas RZ/N1 ethernet subsystem devices | expand |
Hi Clément, On Thu, May 19, 2022 at 5:32 PM Clément Léger <clement.leger@bootlin.com> wrote: > Add bindings for Renesas RZ/N1 Advanced 5 port switch. This switch is > present on Renesas RZ/N1 SoC and was probably provided by MoreThanIP. > This company does not exists anymore and has been bought by Synopsys. > Since this IP can't be find anymore in the Synospsy portfolio, lets use > Renesas as the vendor compatible for this IP. > > Signed-off-by: Clément Léger <clement.leger@bootlin.com> Thanks for your patch! > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml > @@ -0,0 +1,131 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Renesas RZ/N1 Advanced 5 ports ethernet switch > + > +maintainers: > + - Clément Léger <clement.leger@bootlin.com> > + > +description: | > + The advanced 5 ports switch is present on the Renesas RZ/N1 SoC family and > + handles 4 ports + 1 CPU management port. > + > +allOf: > + - $ref: dsa.yaml# > + > +properties: > + compatible: > + items: > + - enum: > + - renesas,r9a06g032-a5psw > + - const: renesas,rzn1-a5psw > + > + reg: > + maxItems: 1 > + > + mdio: > + $ref: /schemas/net/mdio.yaml# > + unevaluatedProperties: false > + > + clocks: > + items: > + - description: AHB clock used for the switch register interface > + - description: Switch system clock > + > + clock-names: > + items: > + - const: hclk > + - const: clk (Good, "clock-names" is present ;-) Missing "power-domains" property. > +examples: > + - | > + #include <dt-bindings/gpio/gpio.h> > + #include <dt-bindings/clock/r9a06g032-sysctrl.h> > + > + switch@44050000 { > + compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw"; > + reg = <0x44050000 0x10000>; > + clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, <&sysctrl R9A06G032_CLK_SWITCH>; > + clock-names = "hclk", "clk"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pins_mdio1>, <&pins_eth3>, <&pins_eth4>; Usually we don't list pinctrl-* properties in examples. The rest LGTM (from an SoC integration PoV), so with the above fixed Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Le Fri, 20 May 2022 09:13:23 +0200, Geert Uytterhoeven <geert@linux-m68k.org> a écrit : > Hi Clément, > > On Thu, May 19, 2022 at 5:32 PM Clément Léger <clement.leger@bootlin.com> wrote: > > Add bindings for Renesas RZ/N1 Advanced 5 port switch. This switch is > > present on Renesas RZ/N1 SoC and was probably provided by MoreThanIP. > > This company does not exists anymore and has been bought by Synopsys. > > Since this IP can't be find anymore in the Synospsy portfolio, lets use > > Renesas as the vendor compatible for this IP. > > > > Signed-off-by: Clément Léger <clement.leger@bootlin.com> > > Thanks for your patch! > > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml > > @@ -0,0 +1,131 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Renesas RZ/N1 Advanced 5 ports ethernet switch > > + > > +maintainers: > > + - Clément Léger <clement.leger@bootlin.com> > > + > > +description: | > > + The advanced 5 ports switch is present on the Renesas RZ/N1 SoC family and > > + handles 4 ports + 1 CPU management port. > > + > > +allOf: > > + - $ref: dsa.yaml# > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - renesas,r9a06g032-a5psw > > + - const: renesas,rzn1-a5psw > > + > > + reg: > > + maxItems: 1 > > + > > + mdio: > > + $ref: /schemas/net/mdio.yaml# > > + unevaluatedProperties: false > > + > > + clocks: > > + items: > > + - description: AHB clock used for the switch register interface > > + - description: Switch system clock > > + > > + clock-names: > > + items: > > + - const: hclk > > + - const: clk > > (Good, "clock-names" is present ;-) > > Missing "power-domains" property. > I do not use pm_runtime* in the switch driver. I should probably do that right ? > > +examples: > > + - | > > + #include <dt-bindings/gpio/gpio.h> > > + #include <dt-bindings/clock/r9a06g032-sysctrl.h> > > + > > + switch@44050000 { > > + compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw"; > > + reg = <0x44050000 0x10000>; > > + clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, <&sysctrl R9A06G032_CLK_SWITCH>; > > + clock-names = "hclk", "clk"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pins_mdio1>, <&pins_eth3>, <&pins_eth4>; > > Usually we don't list pinctrl-* properties in examples. > Acked, I'll remove that. > The rest LGTM (from an SoC integration PoV), so with the above fixed > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
Hi Clément, On Fri, May 20, 2022 at 9:58 AM Clément Léger <clement.leger@bootlin.com> wrote: > Le Fri, 20 May 2022 09:13:23 +0200, > Geert Uytterhoeven <geert@linux-m68k.org> a écrit : > > On Thu, May 19, 2022 at 5:32 PM Clément Léger <clement.leger@bootlin.com> wrote: > > > Add bindings for Renesas RZ/N1 Advanced 5 port switch. This switch is > > > present on Renesas RZ/N1 SoC and was probably provided by MoreThanIP. > > > This company does not exists anymore and has been bought by Synopsys. > > > Since this IP can't be find anymore in the Synospsy portfolio, lets use > > > Renesas as the vendor compatible for this IP. > > > > > > Signed-off-by: Clément Léger <clement.leger@bootlin.com> > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml > > Missing "power-domains" property. > > I do not use pm_runtime* in the switch driver. I should probably do that > right ? For now you don't have to. But I think it is a good idea, and it helps if the IP block is ever reused in an SoC with real power areas. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Le Fri, 20 May 2022 10:01:32 +0200, Geert Uytterhoeven <geert@linux-m68k.org> a écrit : > Hi Clément, > > On Fri, May 20, 2022 at 9:58 AM Clément Léger <clement.leger@bootlin.com> wrote: > > Le Fri, 20 May 2022 09:13:23 +0200, > > Geert Uytterhoeven <geert@linux-m68k.org> a écrit : > > > On Thu, May 19, 2022 at 5:32 PM Clément Léger <clement.leger@bootlin.com> wrote: > > > > Add bindings for Renesas RZ/N1 Advanced 5 port switch. This switch is > > > > present on Renesas RZ/N1 SoC and was probably provided by MoreThanIP. > > > > This company does not exists anymore and has been bought by Synopsys. > > > > Since this IP can't be find anymore in the Synospsy portfolio, lets use > > > > Renesas as the vendor compatible for this IP. > > > > > > > > Signed-off-by: Clément Léger <clement.leger@bootlin.com> > > > > --- /dev/null > > > > +++ b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml > > > > Missing "power-domains" property. > > > > I do not use pm_runtime* in the switch driver. I should probably do that > > right ? > > For now you don't have to. But I think it is a good idea, and it helps if the > IP block is ever reused in an SoC with real power areas. Ok, sounds good, I'll probably also set that as required to be compatible with these potentials modifications without breaking the bindings. Thanks, > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
On Thu, 19 May 2022 17:31:00 +0200, Clément Léger wrote: > Add bindings for Renesas RZ/N1 Advanced 5 port switch. This switch is > present on Renesas RZ/N1 SoC and was probably provided by MoreThanIP. > This company does not exists anymore and has been bought by Synopsys. > Since this IP can't be find anymore in the Synospsy portfolio, lets use > Renesas as the vendor compatible for this IP. > > Signed-off-by: Clément Léger <clement.leger@bootlin.com> > --- > .../bindings/net/dsa/renesas,rzn1-a5psw.yaml | 131 ++++++++++++++++++ > 1 file changed, 131 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml new file mode 100644 index 000000000000..e3ab1cf1575d --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 Advanced 5 ports ethernet switch + +maintainers: + - Clément Léger <clement.leger@bootlin.com> + +description: | + The advanced 5 ports switch is present on the Renesas RZ/N1 SoC family and + handles 4 ports + 1 CPU management port. + +allOf: + - $ref: dsa.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r9a06g032-a5psw + - const: renesas,rzn1-a5psw + + reg: + maxItems: 1 + + mdio: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + + clocks: + items: + - description: AHB clock used for the switch register interface + - description: Switch system clock + + clock-names: + items: + - const: hclk + - const: clk + + ethernet-ports: + type: object + properties: + '#address-cells': + const: 1 + '#size-cells': + const: 0 + + patternProperties: + "^(ethernet-)?port@[0-4]$": + type: object + description: Ethernet switch ports + + properties: + pcs-handle: + description: + phandle pointing to a PCS sub-node compatible with + renesas,rzn1-miic.yaml# + $ref: /schemas/types.yaml#/definitions/phandle + +unevaluatedProperties: false + +required: + - compatible + - reg + - clocks + - clock-names + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/r9a06g032-sysctrl.h> + + switch@44050000 { + compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw"; + reg = <0x44050000 0x10000>; + clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, <&sysctrl R9A06G032_CLK_SWITCH>; + clock-names = "hclk", "clk"; + pinctrl-names = "default"; + pinctrl-0 = <&pins_mdio1>, <&pins_eth3>, <&pins_eth4>; + + dsa,member = <0 0>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + phy-handle = <&switch0phy3>; + pcs-handle = <&mii_conv4>; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-handle = <&switch0phy1>; + pcs-handle = <&mii_conv3>; + }; + + port@4 { + reg = <4>; + ethernet = <&gmac1>; + label = "cpu"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio0a 2 GPIO_ACTIVE_HIGH>; + reset-delay-us = <15>; + clock-frequency = <2500000>; + + switch0phy1: ethernet-phy@1{ + reg = <1>; + }; + + switch0phy3: ethernet-phy@3{ + reg = <3>; + }; + }; + };
Add bindings for Renesas RZ/N1 Advanced 5 port switch. This switch is present on Renesas RZ/N1 SoC and was probably provided by MoreThanIP. This company does not exists anymore and has been bought by Synopsys. Since this IP can't be find anymore in the Synospsy portfolio, lets use Renesas as the vendor compatible for this IP. Signed-off-by: Clément Léger <clement.leger@bootlin.com> --- .../bindings/net/dsa/renesas,rzn1-a5psw.yaml | 131 ++++++++++++++++++ 1 file changed, 131 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml