Message ID | 20220509102204.62389-3-likexu@tencent.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [1/3] KVM: x86/pmu: Ignore pmu->global_ctrl check if vPMU doesn't support global_ctrl | expand |
On 5/9/22 12:22, Like Xu wrote: > In commit c51eb52b8f98 ("KVM: x86: Add support for AMD Core Perf Extension > in guest"), the entry "case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5 " is > introduced asymmetrically into kvm_get_msr_common(), ignoring the set part. > > The missing guest PERFCTR_CORE cpuid check from the above commit leads to > the commit c28fa560c5bb ("KVM: x86/vPMU: Forbid reading from MSR_F15H_PERF > MSRs when guest doesn't have X86_FEATURE_PERFCTR_CORE"), but it simply > duplicates the default entry at the end of the switch statement explicitly. > > Removing the PERFCTR_CORE MSRs entry in kvm_get_msr_common() thoroughly > would be more maintainable, as we did for the same group of MSRs in the > kvm_set_msr_common() at the very beginning when the feature was enabled. The code and the commit message suggest that some guests are expecting a #GP, and complain if they don't get it. Paolo
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 4790f0d7d40b..2b9089701ef5 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -3841,13 +3841,6 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */ msr_info->data = 0; break; - case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: - if (kvm_pmu_is_valid_msr(vcpu, msr_info->index)) - return kvm_pmu_get_msr(vcpu, msr_info); - if (!msr_info->host_initiated) - return 1; - msr_info->data = 0; - break; case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3: case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1: