| Message ID | YoTqwpfrodveJ7CR@Sun (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: add zicsr/zifencei to isa_string | expand |
This patch could work successfully in qemu. With command "cat /proc/device-tree/cpus/cpu@0/riscv\,isa", string "zicsr" and "zifencei" could be found in linux device tree.
Tested-by: Jiatai He <jiatai2021@iscas.ac.cn>
On Wed, May 18, 2022 at 10:50 PM Hongren (Zenithal) Zheng <i@zenithal.me> wrote: > > Zicsr/Zifencei is not in 'I' since ISA version 20190608, > thus to fully express the capability of the CPU, > they should be exposed in isa_string. > > Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> > --- > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6d01569cad..61fa9b97a4 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1027,6 +1027,8 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) > * extensions by an underscore. > */ > struct isa_ext_data isa_edata_arr[] = { > + ISA_EDATA_ENTRY(zicsr, ext_icsr), > + ISA_EDATA_ENTRY(zifencei, ext_ifencei), Shouldn't we have a spec version check here? Alistair > ISA_EDATA_ENTRY(zfh, ext_zfh), > ISA_EDATA_ENTRY(zfhmin, ext_zfhmin), > ISA_EDATA_ENTRY(zfinx, ext_zfinx), > -- > 2.35.1 > >
On Mon, May 23, 2022 at 09:22:15AM +1000, Alistair Francis wrote: > On Wed, May 18, 2022 at 10:50 PM Hongren (Zenithal) Zheng <i@zenithal.me> wrote: > > > > Zicsr/Zifencei is not in 'I' since ISA version 20190608, > > thus to fully express the capability of the CPU, > > they should be exposed in isa_string. > > > > Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> > > --- > > target/riscv/cpu.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 6d01569cad..61fa9b97a4 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -1027,6 +1027,8 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) > > * extensions by an underscore. > > */ > > struct isa_ext_data isa_edata_arr[] = { > > + ISA_EDATA_ENTRY(zicsr, ext_icsr), > > + ISA_EDATA_ENTRY(zifencei, ext_ifencei), > > Shouldn't we have a spec version check here? I think that can be done, but most of the time it is not necessary. For old specs, the "short-isa-string" can be a workaround. This patch is actually a follow-up of "target/riscv: Change "G" expansion" https://github.com/alistair23/qemu/commit/72bd25b7b88d0536bfb5666990e296587d4057a5 where "G" is expanded with "zicsr"/"zifencei" without checking unpriv spec version. From the summary from Kito from gnu toolchain https://lkml.org/lkml/2022/1/24/537 we know that there are at least 3 formally released unpriv specs: 2.2, 20190608 and 20191213, and frequent informal release from https://github.com/riscv/riscv-isa-manual/releases If we add a spec check, we need to add a PROP_STRING and and parse the version. We then need an enum like PRIV_VERSION_1_12_0 and we needs to g_strcmp0 in riscv_cpu_realize, just as what priv spec had done. And we need to define a default unpriv spec version, which should be 20191213. I can add a separate patch for it if you do think it is necessary. If the guest does want old spec version, I think the recently added "short-isa-string" option from Tsukasa OI is suitable. Instead of -cpu rv64,unpriv_spec=2.2 they can just use -cpu rv64,short-isa-string=true to solve the issue. Cc Tsukasa OI > > Alistair > > > ISA_EDATA_ENTRY(zfh, ext_zfh), > > ISA_EDATA_ENTRY(zfhmin, ext_zfhmin), > > ISA_EDATA_ENTRY(zfinx, ext_zfinx), > > -- > > 2.35.1 > > > >
On Tue, May 24, 2022 at 2:51 AM Hongren (Zenithal) Zheng <i@zenithal.me> wrote: > > On Mon, May 23, 2022 at 09:22:15AM +1000, Alistair Francis wrote: > > On Wed, May 18, 2022 at 10:50 PM Hongren (Zenithal) Zheng <i@zenithal.me> wrote: > > > > > > Zicsr/Zifencei is not in 'I' since ISA version 20190608, > > > thus to fully express the capability of the CPU, > > > they should be exposed in isa_string. > > > > > > Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> > > > --- > > > target/riscv/cpu.c | 2 ++ > > > 1 file changed, 2 insertions(+) > > > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > > index 6d01569cad..61fa9b97a4 100644 > > > --- a/target/riscv/cpu.c > > > +++ b/target/riscv/cpu.c > > > @@ -1027,6 +1027,8 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) > > > * extensions by an underscore. > > > */ > > > struct isa_ext_data isa_edata_arr[] = { > > > + ISA_EDATA_ENTRY(zicsr, ext_icsr), > > > + ISA_EDATA_ENTRY(zifencei, ext_ifencei), > > > > Shouldn't we have a spec version check here? > > I think that can be done, but most of the time it is not necessary. > For old specs, the "short-isa-string" can be a workaround. > > This patch is actually a follow-up of "target/riscv: Change "G" expansion" > https://github.com/alistair23/qemu/commit/72bd25b7b88d0536bfb5666990e296587d4057a5 > where "G" is expanded with "zicsr"/"zifencei" without checking > unpriv spec version. > > From the summary from Kito from gnu toolchain > https://lkml.org/lkml/2022/1/24/537 > we know that there are at least 3 formally released unpriv specs: > 2.2, 20190608 and 20191213, and frequent informal release from > https://github.com/riscv/riscv-isa-manual/releases > > If we add a spec check, we need to add a PROP_STRING and > and parse the version. We then need an enum like > PRIV_VERSION_1_12_0 and we needs to g_strcmp0 > in riscv_cpu_realize, just as what priv spec had done. > > And we need to define a default unpriv spec version, which > should be 20191213. > > I can add a separate patch for it if you do think it is necessary. > > If the guest does want old spec version, I think the recently added > "short-isa-string" option from Tsukasa OI is suitable. > Instead of -cpu rv64,unpriv_spec=2.2 they can just use > -cpu rv64,short-isa-string=true to solve the issue. Ok, fair point Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > > Cc Tsukasa OI > > > > > Alistair > > > > > ISA_EDATA_ENTRY(zfh, ext_zfh), > > > ISA_EDATA_ENTRY(zfhmin, ext_zfhmin), > > > ISA_EDATA_ENTRY(zfinx, ext_zfinx), > > > -- > > > 2.35.1 > > > > > >
On Wed, May 18, 2022 at 10:50 PM Hongren (Zenithal) Zheng <i@zenithal.me> wrote: > > Zicsr/Zifencei is not in 'I' since ISA version 20190608, > thus to fully express the capability of the CPU, > they should be exposed in isa_string. > > Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6d01569cad..61fa9b97a4 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1027,6 +1027,8 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) > * extensions by an underscore. > */ > struct isa_ext_data isa_edata_arr[] = { > + ISA_EDATA_ENTRY(zicsr, ext_icsr), > + ISA_EDATA_ENTRY(zifencei, ext_ifencei), > ISA_EDATA_ENTRY(zfh, ext_zfh), > ISA_EDATA_ENTRY(zfhmin, ext_zfhmin), > ISA_EDATA_ENTRY(zfinx, ext_zfinx), > -- > 2.35.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6d01569cad..61fa9b97a4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1027,6 +1027,8 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) * extensions by an underscore. */ struct isa_ext_data isa_edata_arr[] = { + ISA_EDATA_ENTRY(zicsr, ext_icsr), + ISA_EDATA_ENTRY(zifencei, ext_ifencei), ISA_EDATA_ENTRY(zfh, ext_zfh), ISA_EDATA_ENTRY(zfhmin, ext_zfhmin), ISA_EDATA_ENTRY(zfinx, ext_zfinx),
Zicsr/Zifencei is not in 'I' since ISA version 20190608, thus to fully express the capability of the CPU, they should be exposed in isa_string. Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+)