Message ID | 20220523060056.24396-18-rex-bc.chen@mediatek.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Cleanup MediaTek clk reset drivers and support SoCs | expand |
Il 23/05/22 08:00, Rex-BC Chen ha scritto: > To support reset of infra_ao, add the index of infra_ao reset of > thermal/svs for MT8186. > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > Acked-by: Rob Herring <robh@kernel.org> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Rex, sorry but you've probably misunderstood Nicolas' Tested-by... he has tested these on MT8192, so his T-b tag is not applicable to MT8186, MT8195. Anyway: Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
On Mon, 2022-05-23 at 11:05 +0200, AngeloGioacchino Del Regno wrote: > Il 23/05/22 08:00, Rex-BC Chen ha scritto: > > To support reset of infra_ao, add the index of infra_ao reset of > > thermal/svs for MT8186. > > > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > > Acked-by: Rob Herring <robh@kernel.org> > > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > > Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > > Rex, sorry but you've probably misunderstood Nicolas' Tested-by... he > has > tested these on MT8192, so his T-b tag is not applicable to MT8186, > MT8195. > > Anyway: > > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > oh.. Sorry for this. I wil resend v8 to remove them. BRs, Rex
diff --git a/include/dt-bindings/reset/mt8186-resets.h b/include/dt-bindings/reset/mt8186-resets.h index 5f850370c42c..2e9029c22f38 100644 --- a/include/dt-bindings/reset/mt8186-resets.h +++ b/include/dt-bindings/reset/mt8186-resets.h @@ -7,6 +7,7 @@ #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8186 #define _DT_BINDINGS_RESET_CONTROLLER_MT8186 +/* TOPRGU resets */ #define MT8186_TOPRGU_INFRA_SW_RST 0 #define MT8186_TOPRGU_MM_SW_RST 1 #define MT8186_TOPRGU_MFG_SW_RST 2 @@ -33,4 +34,8 @@ /* MMSYS resets */ #define MT8186_MMSYS_SW0_RST_B_DISP_DSI0 19 +/* INFRA resets */ +#define MT8186_INFRA_THERMAL_CTRL_RST 0 +#define MT8186_INFRA_PTP_CTRL_RST 1 + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */