diff mbox series

[v16,3/4] dts: arm64: mt8183: add Mediatek MDP3 nodes

Message ID 20220520083006.27789-4-moudy.ho@mediatek.com (mailing list archive)
State New, archived
Headers show
Series media: mediatek: support mdp3 on mt8183 platform | expand

Commit Message

Moudy Ho (何宗原) May 20, 2022, 8:30 a.m. UTC 
Add device nodes for Media Data Path 3 (MDP3) modules.

Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 79 +++++++++++++++++++++++-
 1 file changed, 78 insertions(+), 1 deletion(-)

Comments

AngeloGioacchino Del Regno May 23, 2022, 3:31 p.m. UTC | #1 
Il 20/05/22 10:30, Moudy Ho ha scritto:
> Add device nodes for Media Data Path 3 (MDP3) modules.
> 
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8183.dtsi | 79 +++++++++++++++++++++++-
>   1 file changed, 78 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index fc6ac2a46324..5b6c18f51787 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -1389,6 +1389,50 @@
>   			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>   		};
>   
> +		mdp3_rdma0: mdp3-rdma0@14001000 {

Are these phandles necessary?
I don't think that any machine will ever override these... and in case this will be
needed in the future, we can always add them later.

> +			compatible = "mediatek,mt8183-mdp3-rdma";
> +			reg = <0 0x14001000 0 0x1000>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
> +			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> +				 <&mmsys CLK_MM_MDP_RSZ1>;
> +			iommus = <&iommu M4U_PORT_MDP_RDMA0>;
> +			mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
> +				 <&gce 21 CMDQ_THR_PRIO_LOWEST 0>;
> +		};
> +
> +		mdp3_rsz0: mdp3-rsz0@14003000 {
> +			compatible = "mediatek,mt8183-mdp3-rsz";
> +			reg = <0 0x14003000 0 0x1000>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
> +			clocks = <&mmsys CLK_MM_MDP_RSZ0>;
> +		};
> +
> +		mdp3_rsz1: mdp3-rsz1@14004000 {
> +			compatible = "mediatek,mt8183-mdp3-rsz";
> +			reg = <0 0x14004000 0 0x1000>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
> +			clocks = <&mmsys CLK_MM_MDP_RSZ1>;
> +		};
> +
> +		mdp3_wrot0: mdp3-wrot0@14005000 {
> +			compatible = "mediatek,mt8183-mdp3-wrot";
> +			reg = <0 0x14005000 0 0x1000>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
> +			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_MDP_WROT0>;
> +			iommus = <&iommu M4U_PORT_MDP_WROT0>;
> +		};
> +
> +		mdp3_wdma: mdp3-wdma@14006000 {
> +			compatible = "mediatek,mt8183-mdp3-wdma";
> +			reg = <0 0x14006000 0 0x1000>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
> +			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> +			clocks = <&mmsys CLK_MM_MDP_WDMA0>;
> +			iommus = <&iommu M4U_PORT_MDP_WDMA0>;
> +		};
> +
>   		ovl0: ovl@14008000 {
>   			compatible = "mediatek,mt8183-disp-ovl";
>   			reg = <0 0x14008000 0 0x1000>;
> @@ -1513,7 +1557,33 @@
>   			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
>   			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
>   			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
> -					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
> +					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>,
> +					      <CMDQ_EVENT_MDP_RDMA0_SOF>,
> +					      <CMDQ_EVENT_MDP_RDMA0_EOF>,
> +					      <CMDQ_EVENT_MDP_RSZ0_SOF>,
> +					      <CMDQ_EVENT_MDP_RSZ1_SOF>,
> +					      <CMDQ_EVENT_MDP_TDSHP_SOF>,
> +					      <CMDQ_EVENT_MDP_WROT0_SOF>,
> +					      <CMDQ_EVENT_MDP_WROT0_EOF>,
> +					      <CMDQ_EVENT_MDP_WDMA0_SOF>,
> +					      <CMDQ_EVENT_MDP_WDMA0_EOF>,
> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>,
> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>,
> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>,
> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>,
> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>,
> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>,
> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>,
> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>,
> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>,
> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>,
> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>,
> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>,
> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>,
> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>,
> +					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>,
> +					      <CMDQ_EVENT_WPE_A_DONE>,
> +					      <CMDQ_EVENT_SPE_B_DONE>;
>   			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
>   		};
>   
> @@ -1538,6 +1608,13 @@
>   			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
>   		};
>   
> +		mdp3_ccorr: mdp3-ccorr@1401c000 {

Same comment applies here too.

Cheers,
Angelo

> +			compatible = "mediatek,mt8183-mdp3-ccorr";
> +			reg = <0 0x1401c000 0 0x1000>;
> +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
> +			clocks = <&mmsys CLK_MM_MDP_CCORR>;
> +		};
> +
>   		imgsys: syscon@15020000 {
>   			compatible = "mediatek,mt8183-imgsys", "syscon";
>   			reg = <0 0x15020000 0 0x1000>;
Moudy Ho (何宗原) May 27, 2022, 9:15 a.m. UTC | #2 
On Mon, 2022-05-23 at 17:31 +0200, AngeloGioacchino Del Regno wrote:
> Il 20/05/22 10:30, Moudy Ho ha scritto:
> > Add device nodes for Media Data Path 3 (MDP3) modules.
> > 
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8183.dtsi | 79
> > +++++++++++++++++++++++-
> >   1 file changed, 78 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > index fc6ac2a46324..5b6c18f51787 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > @@ -1389,6 +1389,50 @@
> >   			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0 0x1000>;
> >   		};
> >   
> > +		mdp3_rdma0: mdp3-rdma0@14001000 {
> 
> Are these phandles necessary?
> I don't think that any machine will ever override these... and in
> case this will be
> needed in the future, we can always add them later.
> 

Hi Angelo,

Thanks for the suggestion, I'll remove the phandle in next version.

Regards,
Moudy
> > +			compatible = "mediatek,mt8183-mdp3-rdma";
> > +			reg = <0 0x14001000 0 0x1000>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x1000 0x1000>;
> > +			power-domains = <&spm
> > MT8183_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> > +				 <&mmsys CLK_MM_MDP_RSZ1>;
> > +			iommus = <&iommu M4U_PORT_MDP_RDMA0>;
> > +			mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
> > +				 <&gce 21 CMDQ_THR_PRIO_LOWEST 0>;
> > +		};
> > +
> > +		mdp3_rsz0: mdp3-rsz0@14003000 {
> > +			compatible = "mediatek,mt8183-mdp3-rsz";
> > +			reg = <0 0x14003000 0 0x1000>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x3000 0x1000>;
> > +			clocks = <&mmsys CLK_MM_MDP_RSZ0>;
> > +		};
> > +
> > +		mdp3_rsz1: mdp3-rsz1@14004000 {
> > +			compatible = "mediatek,mt8183-mdp3-rsz";
> > +			reg = <0 0x14004000 0 0x1000>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x4000 0x1000>;
> > +			clocks = <&mmsys CLK_MM_MDP_RSZ1>;
> > +		};
> > +
> > +		mdp3_wrot0: mdp3-wrot0@14005000 {
> > +			compatible = "mediatek,mt8183-mdp3-wrot";
> > +			reg = <0 0x14005000 0 0x1000>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x5000 0x1000>;
> > +			power-domains = <&spm
> > MT8183_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_MDP_WROT0>;
> > +			iommus = <&iommu M4U_PORT_MDP_WROT0>;
> > +		};
> > +
> > +		mdp3_wdma: mdp3-wdma@14006000 {
> > +			compatible = "mediatek,mt8183-mdp3-wdma";
> > +			reg = <0 0x14006000 0 0x1000>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0x6000 0x1000>;
> > +			power-domains = <&spm
> > MT8183_POWER_DOMAIN_DISP>;
> > +			clocks = <&mmsys CLK_MM_MDP_WDMA0>;
> > +			iommus = <&iommu M4U_PORT_MDP_WDMA0>;
> > +		};
> > +
> >   		ovl0: ovl@14008000 {
> >   			compatible = "mediatek,mt8183-disp-ovl";
> >   			reg = <0 0x14008000 0 0x1000>;
> > @@ -1513,7 +1557,33 @@
> >   			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
> >   			power-domains = <&spm
> > MT8183_POWER_DOMAIN_DISP>;
> >   			mediatek,gce-events =
> > <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
> > -					      <CMDQ_EVENT_MUTEX_STREAM_
> > DONE1>;
> > +					      <CMDQ_EVENT_MUTEX_STREAM_
> > DONE1>,
> > +					      <CMDQ_EVENT_MDP_RDMA0_SOF
> > >,
> > +					      <CMDQ_EVENT_MDP_RDMA0_EOF
> > >,
> > +					      <CMDQ_EVENT_MDP_RSZ0_SOF>
> > ,
> > +					      <CMDQ_EVENT_MDP_RSZ1_SOF>
> > ,
> > +					      <CMDQ_EVENT_MDP_TDSHP_SOF
> > >,
> > +					      <CMDQ_EVENT_MDP_WROT0_SOF
> > >,
> > +					      <CMDQ_EVENT_MDP_WROT0_EOF
> > >,
> > +					      <CMDQ_EVENT_MDP_WDMA0_SOF
> > >,
> > +					      <CMDQ_EVENT_MDP_WDMA0_EOF
> > >,
> > +					      <CMDQ_EVENT_ISP_FRAME_DON
> > E_P2_0>,
> > +					      <CMDQ_EVENT_ISP_FRAME_DON
> > E_P2_1>,
> > +					      <CMDQ_EVENT_ISP_FRAME_DON
> > E_P2_2>,
> > +					      <CMDQ_EVENT_ISP_FRAME_DON
> > E_P2_3>,
> > +					      <CMDQ_EVENT_ISP_FRAME_DON
> > E_P2_4>,
> > +					      <CMDQ_EVENT_ISP_FRAME_DON
> > E_P2_5>,
> > +					      <CMDQ_EVENT_ISP_FRAME_DON
> > E_P2_6>,
> > +					      <CMDQ_EVENT_ISP_FRAME_DON
> > E_P2_7>,
> > +					      <CMDQ_EVENT_ISP_FRAME_DON
> > E_P2_8>,
> > +					      <CMDQ_EVENT_ISP_FRAME_DON
> > E_P2_9>,
> > +					      <CMDQ_EVENT_ISP_FRAME_DON
> > E_P2_10>,
> > +					      <CMDQ_EVENT_ISP_FRAME_DON
> > E_P2_11>,
> > +					      <CMDQ_EVENT_ISP_FRAME_DON
> > E_P2_12>,
> > +					      <CMDQ_EVENT_ISP_FRAME_DON
> > E_P2_13>,
> > +					      <CMDQ_EVENT_ISP_FRAME_DON
> > E_P2_14>,
> > +					      <CMDQ_EVENT_WPE_A_DONE>,
> > +					      <CMDQ_EVENT_SPE_B_DONE>;
> >   			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX
> > 0x6000 0x1000>;
> >   		};
> >   
> > @@ -1538,6 +1608,13 @@
> >   			power-domains = <&spm
> > MT8183_POWER_DOMAIN_DISP>;
> >   		};
> >   
> > +		mdp3_ccorr: mdp3-ccorr@1401c000 {
> 
> Same comment applies here too.
> 
> Cheers,
> Angelo
> 
> > +			compatible = "mediatek,mt8183-mdp3-ccorr";
> > +			reg = <0 0x1401c000 0 0x1000>;
> > +			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX
> > 0xc000 0x1000>;
> > +			clocks = <&mmsys CLK_MM_MDP_CCORR>;
> > +		};
> > +
> >   		imgsys: syscon@15020000 {
> >   			compatible = "mediatek,mt8183-imgsys",
> > "syscon";
> >   			reg = <0 0x15020000 0 0x1000>;
> 
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index fc6ac2a46324..5b6c18f51787 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1389,6 +1389,50 @@ 
 			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
 		};
 
+		mdp3_rdma0: mdp3-rdma0@14001000 {
+			compatible = "mediatek,mt8183-mdp3-rdma";
+			reg = <0 0x14001000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
+			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+				 <&mmsys CLK_MM_MDP_RSZ1>;
+			iommus = <&iommu M4U_PORT_MDP_RDMA0>;
+			mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
+				 <&gce 21 CMDQ_THR_PRIO_LOWEST 0>;
+		};
+
+		mdp3_rsz0: mdp3-rsz0@14003000 {
+			compatible = "mediatek,mt8183-mdp3-rsz";
+			reg = <0 0x14003000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
+			clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+		};
+
+		mdp3_rsz1: mdp3-rsz1@14004000 {
+			compatible = "mediatek,mt8183-mdp3-rsz";
+			reg = <0 0x14004000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
+			clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+		};
+
+		mdp3_wrot0: mdp3-wrot0@14005000 {
+			compatible = "mediatek,mt8183-mdp3-wrot";
+			reg = <0 0x14005000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_MDP_WROT0>;
+			iommus = <&iommu M4U_PORT_MDP_WROT0>;
+		};
+
+		mdp3_wdma: mdp3-wdma@14006000 {
+			compatible = "mediatek,mt8183-mdp3-wdma";
+			reg = <0 0x14006000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_MDP_WDMA0>;
+			iommus = <&iommu M4U_PORT_MDP_WDMA0>;
+		};
+
 		ovl0: ovl@14008000 {
 			compatible = "mediatek,mt8183-disp-ovl";
 			reg = <0 0x14008000 0 0x1000>;
@@ -1513,7 +1557,33 @@ 
 			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
 			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
-					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
+					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>,
+					      <CMDQ_EVENT_MDP_RDMA0_SOF>,
+					      <CMDQ_EVENT_MDP_RDMA0_EOF>,
+					      <CMDQ_EVENT_MDP_RSZ0_SOF>,
+					      <CMDQ_EVENT_MDP_RSZ1_SOF>,
+					      <CMDQ_EVENT_MDP_TDSHP_SOF>,
+					      <CMDQ_EVENT_MDP_WROT0_SOF>,
+					      <CMDQ_EVENT_MDP_WROT0_EOF>,
+					      <CMDQ_EVENT_MDP_WDMA0_SOF>,
+					      <CMDQ_EVENT_MDP_WDMA0_EOF>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>,
+					      <CMDQ_EVENT_WPE_A_DONE>,
+					      <CMDQ_EVENT_SPE_B_DONE>;
 			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
 		};
 
@@ -1538,6 +1608,13 @@ 
 			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
 		};
 
+		mdp3_ccorr: mdp3-ccorr@1401c000 {
+			compatible = "mediatek,mt8183-mdp3-ccorr";
+			reg = <0 0x1401c000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
+			clocks = <&mmsys CLK_MM_MDP_CCORR>;
+		};
+
 		imgsys: syscon@15020000 {
 			compatible = "mediatek,mt8183-imgsys", "syscon";
 			reg = <0 0x15020000 0 0x1000>;