| Message ID | 20220526035611.4063102-1-peng.fan@oss.nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | dt-bindings: dma: fsl-edma: Convert to DT schema | expand |
On 26/05/2022 05:56, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > Convert the eDMA controller binding to DT schema. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > .../devicetree/bindings/dma/fsl,edma.yaml | 136 ++++++++++++++++++ > .../devicetree/bindings/dma/fsl-edma.txt | 111 -------------- > 2 files changed, 136 insertions(+), 111 deletions(-) > create mode 100644 Documentation/devicetree/bindings/dma/fsl,edma.yaml > delete mode 100644 Documentation/devicetree/bindings/dma/fsl-edma.txt > > diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml > new file mode 100644 > index 000000000000..dbb69aca7d67 > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml > @@ -0,0 +1,136 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/dma/fsl,edma.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Freescale enhanced Direct Memory Access(eDMA) Controller > + > +description: | > + The eDMA channels have multiplex capability by programmble programmable > + memory-mapped registers. channels are split into two groups, called > + DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed > + by any channel of certain group, DMAMUX0 or DMAMUX1, but not both. > + > +maintainers: > + - Peng Fan <peng.fan@nxp.com> > + > +allOf: > + - $ref: "dma-controller.yaml#" > + > +properties: > + compatible: > + oneOf: > + - const: fsl,vf610-edma > + - const: fsl,imx7ulp-edma These should be one enum. > + - items: > + - const: fsl,ls1028a-edma > + - const: fsl,vf610-edma > + > + "#dma-cells": > + const: 2 > + > + dma-channels: > + minItems: 32 > + maxItems: 64 > + > + reg: > + minItems: 2 > + maxItems: 65 Old binding mentions only three regions. Why 65? > + > + interrupts: > + minItems: 2 > + maxItems: 65 The maxItems look weird here. Shouldn't this be 17? This needs its own constraints in allOf:if:then per variant. > + > + clocks: > + maxItems: 2 > + > + big-endian: > + description: | > + If present registers and hardware scatter/gather descriptors of the > + eDMA are implemented in big endian mode, otherwise in little mode. > + type: boolean > + > + interrupt-names: > + items: > + - const: edma-tx > + - const: edma-err Put it next to interrupts. > + > +required: > + - "#dma-cells" > + - compatible > + - reg > + - interrupts > + - clocks > + - dma-channels > + > +if: This should be under allOf and that entire allOf block (with $ref) should be located here. > + properties: > + compatible: > + contains: > + const: fsl,imx7ulp-edma > +then: > + properties: > + clock-names: > + items: > + - const: dma > + - const: dmamux0 > +else: > + properties: > + clock-names: > + items: > + - const: dmamux0 > + - const: dmamux1 > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/clock/vf610-clock.h> > + > + edma0: dma-controller@40018000 { > + #dma-cells = <2>; > + compatible = "fsl,vf610-edma"; > + reg = <0x40018000 0x2000>, > + <0x40024000 0x1000>, > + <0x40025000 0x1000>; > + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, > + <0 9 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "edma-tx", "edma-err"; > + dma-channels = <32>; > + clock-names = "dmamux0", "dmamux1"; > + clocks = <&clks VF610_CLK_DMAMUX0>, <&clks VF610_CLK_DMAMUX1>; > + }; > + > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/clock/imx7ulp-clock.h> > + > + edma1: dma-controller@40080000 { > + #dma-cells = <2>; > + compatible = "fsl,imx7ulp-edma"; > + reg = <0x40080000 0x2000>, > + <0x40210000 0x1000>; > + dma-channels = <32>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, > + /* last is eDMA2-ERR interrupt */ > + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "dma", "dmamux0"; > + clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>; > + }; > diff --git a/Documentation/devicetree/bindings/dma/fsl-edma.txt b/Documentation/devicetree/bindings/dma/fsl-edma.txt > deleted file mode 100644 > index ee1754739b4b..000000000000 > --- a/Documentation/devicetree/bindings/dma/fsl-edma.txt > +++ /dev/null > @@ -1,111 +0,0 @@ > -* Freescale enhanced Direct Memory Access(eDMA) Controller > - > - The eDMA channels have multiplex capability by programmble memory-mapped > -registers. channels are split into two groups, called DMAMUX0 and DMAMUX1, > -specific DMA request source can only be multiplexed by any channel of certain > -group, DMAMUX0 or DMAMUX1, but not both. > - > -* eDMA Controller > -Required properties: > -- compatible : > - - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC > - - "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp > - - "fsl,ls1028a-edma" followed by "fsl,vf610-edma" for eDMA used on the > - LS1028A SoC. > -- reg : Specifies base physical address(s) and size of the eDMA registers. > - The 1st region is eDMA control register's address and size. > - The 2nd and the 3rd regions are programmable channel multiplexing > - control register's address and size. > -- interrupts : A list of interrupt-specifiers, one for each entry in > - interrupt-names on vf610 similar SoC. But for i.mx7ulp per channel > - per transmission interrupt, total 16 channel interrupt and 1 > - error interrupt(located in the last), no interrupt-names list on > - i.mx7ulp for clean on dts. > -- #dma-cells : Must be <2>. > - The 1st cell specifies the DMAMUX(0 for DMAMUX0 and 1 for DMAMUX1). > - Specific request source can only be multiplexed by specific channels > - group called DMAMUX. > - The 2nd cell specifies the request source(slot) ID. > - See the SoC's reference manual for all the supported request sources. > -- dma-channels : Number of channels supported by the controller > -- clock-names : A list of channel group clock names. Should contain: > - "dmamux0" - clock name of mux0 group > - "dmamux1" - clock name of mux1 group > - Note: No dmamux0 on i.mx7ulp, but another 'dma' clk added on i.mx7ulp. > -- clocks : A list of phandle and clock-specifier pairs, one for each entry in > - clock-names. > - > -Optional properties: > -- big-endian: If present registers and hardware scatter/gather descriptors > - of the eDMA are implemented in big endian mode, otherwise in little > - mode. > -- interrupt-names : Should contain the below on vf610 similar SoC but not used > - on i.mx7ulp similar SoC: > - "edma-tx" - the transmission interrupt > - "edma-err" - the error interrupt > - > - > -Examples: > - > -edma0: dma-controller@40018000 { > - #dma-cells = <2>; > - compatible = "fsl,vf610-edma"; > - reg = <0x40018000 0x2000>, > - <0x40024000 0x1000>, > - <0x40025000 0x1000>; > - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, > - <0 9 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "edma-tx", "edma-err"; > - dma-channels = <32>; > - clock-names = "dmamux0", "dmamux1"; > - clocks = <&clks VF610_CLK_DMAMUX0>, > - <&clks VF610_CLK_DMAMUX1>; > -}; /* vf610 */ > - > -edma1: dma-controller@40080000 { > - #dma-cells = <2>; > - compatible = "fsl,imx7ulp-edma"; > - reg = <0x40080000 0x2000>, > - <0x40210000 0x1000>; > - dma-channels = <32>; > - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, > - /* last is eDMA2-ERR interrupt */ > - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; > - clock-names = "dma", "dmamux0"; > - clocks = <&pcc2 IMX7ULP_CLK_DMA1>, > - <&pcc2 IMX7ULP_CLK_DMA_MUX1>; > -}; /* i.mx7ulp */ > - > -* DMA clients > -DMA client drivers that uses the DMA function must use the format described > -in the dma.txt file, using a two-cell specifier for each channel: the 1st > -specifies the channel group(DMAMUX) in which this request can be multiplexed, > -and the 2nd specifies the request source. > - > -Examples: > - > -sai2: sai@40031000 { > - compatible = "fsl,vf610-sai"; > - reg = <0x40031000 0x1000>; > - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; > - clock-names = "sai"; > - clocks = <&clks VF610_CLK_SAI2>; > - dma-names = "tx", "rx"; > - dmas = <&edma0 0 21>, > - <&edma0 0 20>; > -}; Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml new file mode 100644 index 000000000000..dbb69aca7d67 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/fsl,edma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale enhanced Direct Memory Access(eDMA) Controller + +description: | + The eDMA channels have multiplex capability by programmble + memory-mapped registers. channels are split into two groups, called + DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed + by any channel of certain group, DMAMUX0 or DMAMUX1, but not both. + +maintainers: + - Peng Fan <peng.fan@nxp.com> + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + oneOf: + - const: fsl,vf610-edma + - const: fsl,imx7ulp-edma + - items: + - const: fsl,ls1028a-edma + - const: fsl,vf610-edma + + "#dma-cells": + const: 2 + + dma-channels: + minItems: 32 + maxItems: 64 + + reg: + minItems: 2 + maxItems: 65 + + interrupts: + minItems: 2 + maxItems: 65 + + clocks: + maxItems: 2 + + big-endian: + description: | + If present registers and hardware scatter/gather descriptors of the + eDMA are implemented in big endian mode, otherwise in little mode. + type: boolean + + interrupt-names: + items: + - const: edma-tx + - const: edma-err + +required: + - "#dma-cells" + - compatible + - reg + - interrupts + - clocks + - dma-channels + +if: + properties: + compatible: + contains: + const: fsl,imx7ulp-edma +then: + properties: + clock-names: + items: + - const: dma + - const: dmamux0 +else: + properties: + clock-names: + items: + - const: dmamux0 + - const: dmamux1 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/vf610-clock.h> + + edma0: dma-controller@40018000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x40018000 0x2000>, + <0x40024000 0x1000>, + <0x40025000 0x1000>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, + <0 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma-tx", "edma-err"; + dma-channels = <32>; + clock-names = "dmamux0", "dmamux1"; + clocks = <&clks VF610_CLK_DMAMUX0>, <&clks VF610_CLK_DMAMUX1>; + }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/imx7ulp-clock.h> + + edma1: dma-controller@40080000 { + #dma-cells = <2>; + compatible = "fsl,imx7ulp-edma"; + reg = <0x40080000 0x2000>, + <0x40210000 0x1000>; + dma-channels = <32>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + /* last is eDMA2-ERR interrupt */ + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dma", "dmamux0"; + clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>; + }; diff --git a/Documentation/devicetree/bindings/dma/fsl-edma.txt b/Documentation/devicetree/bindings/dma/fsl-edma.txt deleted file mode 100644 index ee1754739b4b..000000000000 --- a/Documentation/devicetree/bindings/dma/fsl-edma.txt +++ /dev/null @@ -1,111 +0,0 @@ -* Freescale enhanced Direct Memory Access(eDMA) Controller - - The eDMA channels have multiplex capability by programmble memory-mapped -registers. channels are split into two groups, called DMAMUX0 and DMAMUX1, -specific DMA request source can only be multiplexed by any channel of certain -group, DMAMUX0 or DMAMUX1, but not both. - -* eDMA Controller -Required properties: -- compatible : - - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC - - "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp - - "fsl,ls1028a-edma" followed by "fsl,vf610-edma" for eDMA used on the - LS1028A SoC. -- reg : Specifies base physical address(s) and size of the eDMA registers. - The 1st region is eDMA control register's address and size. - The 2nd and the 3rd regions are programmable channel multiplexing - control register's address and size. -- interrupts : A list of interrupt-specifiers, one for each entry in - interrupt-names on vf610 similar SoC. But for i.mx7ulp per channel - per transmission interrupt, total 16 channel interrupt and 1 - error interrupt(located in the last), no interrupt-names list on - i.mx7ulp for clean on dts. -- #dma-cells : Must be <2>. - The 1st cell specifies the DMAMUX(0 for DMAMUX0 and 1 for DMAMUX1). - Specific request source can only be multiplexed by specific channels - group called DMAMUX. - The 2nd cell specifies the request source(slot) ID. - See the SoC's reference manual for all the supported request sources. -- dma-channels : Number of channels supported by the controller -- clock-names : A list of channel group clock names. Should contain: - "dmamux0" - clock name of mux0 group - "dmamux1" - clock name of mux1 group - Note: No dmamux0 on i.mx7ulp, but another 'dma' clk added on i.mx7ulp. -- clocks : A list of phandle and clock-specifier pairs, one for each entry in - clock-names. - -Optional properties: -- big-endian: If present registers and hardware scatter/gather descriptors - of the eDMA are implemented in big endian mode, otherwise in little - mode. -- interrupt-names : Should contain the below on vf610 similar SoC but not used - on i.mx7ulp similar SoC: - "edma-tx" - the transmission interrupt - "edma-err" - the error interrupt - - -Examples: - -edma0: dma-controller@40018000 { - #dma-cells = <2>; - compatible = "fsl,vf610-edma"; - reg = <0x40018000 0x2000>, - <0x40024000 0x1000>, - <0x40025000 0x1000>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, - <0 9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma-tx", "edma-err"; - dma-channels = <32>; - clock-names = "dmamux0", "dmamux1"; - clocks = <&clks VF610_CLK_DMAMUX0>, - <&clks VF610_CLK_DMAMUX1>; -}; /* vf610 */ - -edma1: dma-controller@40080000 { - #dma-cells = <2>; - compatible = "fsl,imx7ulp-edma"; - reg = <0x40080000 0x2000>, - <0x40210000 0x1000>; - dma-channels = <32>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - /* last is eDMA2-ERR interrupt */ - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "dma", "dmamux0"; - clocks = <&pcc2 IMX7ULP_CLK_DMA1>, - <&pcc2 IMX7ULP_CLK_DMA_MUX1>; -}; /* i.mx7ulp */ - -* DMA clients -DMA client drivers that uses the DMA function must use the format described -in the dma.txt file, using a two-cell specifier for each channel: the 1st -specifies the channel group(DMAMUX) in which this request can be multiplexed, -and the 2nd specifies the request source. - -Examples: - -sai2: sai@40031000 { - compatible = "fsl,vf610-sai"; - reg = <0x40031000 0x1000>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "sai"; - clocks = <&clks VF610_CLK_SAI2>; - dma-names = "tx", "rx"; - dmas = <&edma0 0 21>, - <&edma0 0 20>; -};