| Message ID | 20220608161405.729964-2-apatel@ventanamicro.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | QEMU RISC-V nested virtualization fixes | expand |
On Thu, Jun 9, 2022 at 12:15 AM Anup Patel <apatel@ventanamicro.com> wrote: > > The riscv_cpu_realize() sets priv spec verion to v1.12 when it is typo: version > when "env->priv_ver == 0" (i.e. default v1.10) because the enum > value of priv spec v1.10 is zero. > > Due to above issue, the sifive_u machine will see priv spec v1.12 > instead of priv spec v1.10. > > To fix this issue, we set latest priv spec version (i.e. v1.12) > for base rv64/rv32 cpu and riscv_cpu_realize() will override priv > spec version only when "cpu->cfg.priv_spec != NULL". > > Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > Reviewed-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > Reviewed-by: Atish Patra <atishp@rivosinc.com> > --- > target/riscv/cpu.c | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > Otherwise, Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0497af45cc..9f9c27a3f5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -169,6 +169,8 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); + /* Set latest version of privileged specification */ + set_priv_version(env, PRIV_VERSION_1_12_0); } static void rv64_sifive_u_cpu_init(Object *obj) @@ -204,6 +206,8 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); + /* Set latest version of privileged specification */ + set_priv_version(env, PRIV_VERSION_1_12_0); } static void rv32_sifive_u_cpu_init(Object *obj) @@ -509,7 +513,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) CPURISCVState *env = &cpu->env; RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); CPUClass *cc = CPU_CLASS(mcc); - int priv_version = 0; + int priv_version = -1; Error *local_err = NULL; cpu_exec_realizefn(cs, &local_err); @@ -533,10 +537,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } - if (priv_version) { + if (priv_version >= PRIV_VERSION_1_10_0) { set_priv_version(env, priv_version); - } else if (!env->priv_ver) { - set_priv_version(env, PRIV_VERSION_1_12_0); } if (cpu->cfg.mmu) {
The riscv_cpu_realize() sets priv spec verion to v1.12 when it is when "env->priv_ver == 0" (i.e. default v1.10) because the enum value of priv spec v1.10 is zero. Due to above issue, the sifive_u machine will see priv spec v1.12 instead of priv spec v1.10. To fix this issue, we set latest priv spec version (i.e. v1.12) for base rv64/rv32 cpu and riscv_cpu_realize() will override priv spec version only when "cpu->cfg.priv_spec != NULL". Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> --- target/riscv/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-)