diff mbox series

[v6,2/3] PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*

Message ID f452d0d28482462557485805d708b9adb9e0f6c0.1644234441.git.baruch@tkos.co.il (mailing list archive)
State Not Applicable
Headers show
Series PCI: IPQ6018 platform support | expand

Commit Message

Baruch Siach Feb. 7, 2022, 2:51 p.m. UTC 
From: Baruch Siach <baruch.siach@siklu.com>

The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use
PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better
describe its meaning.

Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

Comments

Pali Rohár June 8, 2022, 11 p.m. UTC | #1 
On Monday 07 February 2022 16:51:25 Baruch Siach wrote:
> From: Baruch Siach <baruch.siach@siklu.com>
> 
> The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use
> PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better
> describe its meaning.
> 
> Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++--
>  1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index c19cd506ed3f..01e58b057d2a 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -69,7 +69,18 @@
>  #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1		0x81c
>  #define CFG_BRIDGE_SB_INIT			BIT(0)
>  
> -#define PCIE_CAP_LINK1_VAL			0x2FD7F
> +#define PCIE_CAP_SLOT_POWER_LIMIT_VAL		0x7D00
> +#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE		0x8000

Hello!

Please do not use hardcoded values for slot power limit value and scale
numbers. There are macros PCI_EXP_SLTCAP_SPLV and PCI_EXP_SLTCAP_SPLS
for composing mask:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/uapi/linux/pci_regs.h?h=v5.19-rc1#n593
Which could be used together with FIELD_PREP(). See e.g. aardvark commit:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0d5b8c298545c827ca9f2461b2655277ce0aef79

And the important information: Slot power limit is board specific and
depends on how power supply and power regulators are designed. So slot
power limit **cannot** be hardcoded in driver. Instead this value should
be read from device tree file for the current board.

There is a new kernel function of_pci_get_slot_power_limit() which reads
it and compose PCIe slot power limit value and scale numbers. See:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/of.c?h=v5.19-rc1#n631

> +#define PCIE_CAP_SLOT_VAL			(PCI_EXP_SLTCAP_ABP | \
> +						PCI_EXP_SLTCAP_PCP | \
> +						PCI_EXP_SLTCAP_MRLSP | \
> +						PCI_EXP_SLTCAP_AIP | \
> +						PCI_EXP_SLTCAP_PIP | \
> +						PCI_EXP_SLTCAP_HPS | \
> +						PCI_EXP_SLTCAP_HPC | \
> +						PCI_EXP_SLTCAP_EIP | \
> +						PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
> +						PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
>  
>  #define PCIE20_PARF_Q2A_FLUSH			0x1AC
>  
> @@ -1111,7 +1122,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
>  
>  	writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
>  	writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
> -	writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
> +	writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
>  
>  	val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
>  	val &= ~PCI_EXP_LNKCAP_ASPMS;
> -- 
> 2.34.1
>
Baruch Siach June 9, 2022, 3:27 a.m. UTC | #2 
Hi Pali,

On Thu, Jun 09 2022, Pali Rohár wrote:
> On Monday 07 February 2022 16:51:25 Baruch Siach wrote:
>> From: Baruch Siach <baruch.siach@siklu.com>
>> 
>> The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use
>> PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better
>> describe its meaning.
>> 
>> Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
>> ---
>>  drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++--
>>  1 file changed, 13 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
>> index c19cd506ed3f..01e58b057d2a 100644
>> --- a/drivers/pci/controller/dwc/pcie-qcom.c
>> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
>> @@ -69,7 +69,18 @@
>>  #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1		0x81c
>>  #define CFG_BRIDGE_SB_INIT			BIT(0)
>>  
>> -#define PCIE_CAP_LINK1_VAL			0x2FD7F
>> +#define PCIE_CAP_SLOT_POWER_LIMIT_VAL		0x7D00
>> +#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE		0x8000
>
> Hello!
>
> Please do not use hardcoded values for slot power limit value and scale
> numbers. There are macros PCI_EXP_SLTCAP_SPLV and PCI_EXP_SLTCAP_SPLS
> for composing mask:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/uapi/linux/pci_regs.h?h=v5.19-rc1#n593
> Which could be used together with FIELD_PREP(). See e.g. aardvark commit:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0d5b8c298545c827ca9f2461b2655277ce0aef79

Thanks for the tip.

> And the important information: Slot power limit is board specific and
> depends on how power supply and power regulators are designed. So slot
> power limit **cannot** be hardcoded in driver. Instead this value should
> be read from device tree file for the current board.
>
> There is a new kernel function of_pci_get_slot_power_limit() which reads
> it and compose PCIe slot power limit value and scale numbers. See:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/of.c?h=v5.19-rc1#n631

The 'slot-power-limit-milliwatt' property appears to be undocumented as
of v5.19-rc1.

This patch should make no functional change. I guess we should keep the
default hard-coded driver value for compatibility with existing DTs with
no 'slot-power-limit-milliwatt'.

Thanks,
baruch

>> +#define PCIE_CAP_SLOT_VAL			(PCI_EXP_SLTCAP_ABP | \
>> +						PCI_EXP_SLTCAP_PCP | \
>> +						PCI_EXP_SLTCAP_MRLSP | \
>> +						PCI_EXP_SLTCAP_AIP | \
>> +						PCI_EXP_SLTCAP_PIP | \
>> +						PCI_EXP_SLTCAP_HPS | \
>> +						PCI_EXP_SLTCAP_HPC | \
>> +						PCI_EXP_SLTCAP_EIP | \
>> +						PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
>> +						PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
>>  
>>  #define PCIE20_PARF_Q2A_FLUSH			0x1AC
>>  
>> @@ -1111,7 +1122,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
>>  
>>  	writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
>>  	writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
>> -	writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
>> +	writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
>>  
>>  	val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
>>  	val &= ~PCI_EXP_LNKCAP_ASPMS;
>> -- 
>> 2.34.1
>>
Pali Rohár June 9, 2022, 8:47 a.m. UTC | #3 
On Thursday 09 June 2022 06:27:34 Baruch Siach wrote:
> Hi Pali,
> 
> On Thu, Jun 09 2022, Pali Rohár wrote:
> > On Monday 07 February 2022 16:51:25 Baruch Siach wrote:
> >> From: Baruch Siach <baruch.siach@siklu.com>
> >> 
> >> The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use
> >> PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better
> >> describe its meaning.
> >> 
> >> Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
> >> ---
> >>  drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++--
> >>  1 file changed, 13 insertions(+), 2 deletions(-)
> >> 
> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> >> index c19cd506ed3f..01e58b057d2a 100644
> >> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> >> @@ -69,7 +69,18 @@
> >>  #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1		0x81c
> >>  #define CFG_BRIDGE_SB_INIT			BIT(0)
> >>  
> >> -#define PCIE_CAP_LINK1_VAL			0x2FD7F
> >> +#define PCIE_CAP_SLOT_POWER_LIMIT_VAL		0x7D00
> >> +#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE		0x8000
> >
> > Hello!
> >
> > Please do not use hardcoded values for slot power limit value and scale
> > numbers. There are macros PCI_EXP_SLTCAP_SPLV and PCI_EXP_SLTCAP_SPLS
> > for composing mask:
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/uapi/linux/pci_regs.h?h=v5.19-rc1#n593
> > Which could be used together with FIELD_PREP(). See e.g. aardvark commit:
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0d5b8c298545c827ca9f2461b2655277ce0aef79
> 
> Thanks for the tip.
> 
> > And the important information: Slot power limit is board specific and
> > depends on how power supply and power regulators are designed. So slot
> > power limit **cannot** be hardcoded in driver. Instead this value should
> > be read from device tree file for the current board.
> >
> > There is a new kernel function of_pci_get_slot_power_limit() which reads
> > it and compose PCIe slot power limit value and scale numbers. See:
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/of.c?h=v5.19-rc1#n631
> 
> The 'slot-power-limit-milliwatt' property appears to be undocumented as
> of v5.19-rc1.

slot-power-limit-milliwatt is already documented in DT scheme pci-bus, see:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/pci/pci-bus.yaml

> This patch should make no functional change. I guess we should keep the
> default hard-coded driver value for compatibility with existing DTs with
> no 'slot-power-limit-milliwatt'.
> 
> Thanks,
> baruch
> 
> >> +#define PCIE_CAP_SLOT_VAL			(PCI_EXP_SLTCAP_ABP | \
> >> +						PCI_EXP_SLTCAP_PCP | \
> >> +						PCI_EXP_SLTCAP_MRLSP | \
> >> +						PCI_EXP_SLTCAP_AIP | \
> >> +						PCI_EXP_SLTCAP_PIP | \
> >> +						PCI_EXP_SLTCAP_HPS | \
> >> +						PCI_EXP_SLTCAP_HPC | \
> >> +						PCI_EXP_SLTCAP_EIP | \
> >> +						PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
> >> +						PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
> >>  
> >>  #define PCIE20_PARF_Q2A_FLUSH			0x1AC
> >>  
> >> @@ -1111,7 +1122,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
> >>  
> >>  	writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
> >>  	writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
> >> -	writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
> >> +	writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
> >>  
> >>  	val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
> >>  	val &= ~PCI_EXP_LNKCAP_ASPMS;
> >> -- 
> >> 2.34.1
> >> 
> 
> 
> -- 
>                                                      ~. .~   Tk Open Systems
> =}------------------------------------------------ooO--U--Ooo------------{=
>    - baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
diff mbox series

Patch

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index c19cd506ed3f..01e58b057d2a 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -69,7 +69,18 @@ 
 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1		0x81c
 #define CFG_BRIDGE_SB_INIT			BIT(0)
 
-#define PCIE_CAP_LINK1_VAL			0x2FD7F
+#define PCIE_CAP_SLOT_POWER_LIMIT_VAL		0x7D00
+#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE		0x8000
+#define PCIE_CAP_SLOT_VAL			(PCI_EXP_SLTCAP_ABP | \
+						PCI_EXP_SLTCAP_PCP | \
+						PCI_EXP_SLTCAP_MRLSP | \
+						PCI_EXP_SLTCAP_AIP | \
+						PCI_EXP_SLTCAP_PIP | \
+						PCI_EXP_SLTCAP_HPS | \
+						PCI_EXP_SLTCAP_HPC | \
+						PCI_EXP_SLTCAP_EIP | \
+						PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
+						PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
 
 #define PCIE20_PARF_Q2A_FLUSH			0x1AC
 
@@ -1111,7 +1122,7 @@  static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
 
 	writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
 	writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
-	writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
+	writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
 
 	val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
 	val &= ~PCI_EXP_LNKCAP_ASPMS;