| Message ID | 20220505193143.31826-2-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add CPG wrapper for Renesas RZ/Five SoC | expand |
Hi Prabhakar, Thanks for your patch! On Thu, May 5, 2022 at 9:32 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Renesas RZ/Five SoC has almost the same clock structure compared to the > Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.h header file and just > ammend the RZ/Five CPG clock and reset definitions. amend > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- a/include/dt-bindings/clock/r9a07g043-cpg.h > +++ b/include/dt-bindings/clock/r9a07g043-cpg.h > @@ -108,6 +108,15 @@ > #define R9A07G043_ADC_ADCLK 76 > #define R9A07G043_ADC_PCLK 77 > #define R9A07G043_TSU_PCLK 78 > +#define R9A07G043_NCEPLDM_DM_CLK 79 /* RZ/Five Only */ While NCEPLDM_DM_CLK is listed in the clock list spreadsheet, its control bit is not documented. > +#define R9A07G043_NCEPLDM_ACLK 80 /* RZ/Five Only */ > +#define R9A07G043_NCEPLDM_TCK 81 /* RZ/Five Only */ While NCEPLDM_TCK is listed in the clock list spreadsheet, its control bit is not documented. The rest LGTM, so with the above clarified Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Thank you for the review. On Tue, May 10, 2022 at 3:02 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > Thanks for your patch! > > On Thu, May 5, 2022 at 9:32 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > Renesas RZ/Five SoC has almost the same clock structure compared to the > > Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.h header file and just > > ammend the RZ/Five CPG clock and reset definitions. > > amend > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > --- a/include/dt-bindings/clock/r9a07g043-cpg.h > > +++ b/include/dt-bindings/clock/r9a07g043-cpg.h > > @@ -108,6 +108,15 @@ > > #define R9A07G043_ADC_ADCLK 76 > > #define R9A07G043_ADC_PCLK 77 > > #define R9A07G043_TSU_PCLK 78 > > +#define R9A07G043_NCEPLDM_DM_CLK 79 /* RZ/Five Only */ > > While NCEPLDM_DM_CLK is listed in the clock list spreadsheet, its > control bit is not documented. > > > +#define R9A07G043_NCEPLDM_ACLK 80 /* RZ/Five Only */ > > +#define R9A07G043_NCEPLDM_TCK 81 /* RZ/Five Only */ > > While NCEPLDM_TCK is listed in the clock list spreadsheet, its > control bit is not documented. > I have got the feedback for the above, NCEPLDM_DM_CLK and NCEPLDM_TCK clocks cannot be stopped as a result there are no register bits for it in the HW manual (clock spreadsheet will be updated). I will drop this and send a v2 including your RB. Cheers, Prabhakar > The rest LGTM, so with the above clarified > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
Hi Prabhakar, On Thu, May 19, 2022 at 7:45 AM Lad, Prabhakar <prabhakar.csengg@gmail.com> wrote: > On Tue, May 10, 2022 at 3:02 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > On Thu, May 5, 2022 at 9:32 PM Lad Prabhakar > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > > Renesas RZ/Five SoC has almost the same clock structure compared to the > > > Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.h header file and just > > > ammend the RZ/Five CPG clock and reset definitions. > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > --- a/include/dt-bindings/clock/r9a07g043-cpg.h > > > +++ b/include/dt-bindings/clock/r9a07g043-cpg.h > > > @@ -108,6 +108,15 @@ > > > #define R9A07G043_ADC_ADCLK 76 > > > #define R9A07G043_ADC_PCLK 77 > > > #define R9A07G043_TSU_PCLK 78 > > > +#define R9A07G043_NCEPLDM_DM_CLK 79 /* RZ/Five Only */ > > > > While NCEPLDM_DM_CLK is listed in the clock list spreadsheet, its > > control bit is not documented. > > > > > +#define R9A07G043_NCEPLDM_ACLK 80 /* RZ/Five Only */ > > > +#define R9A07G043_NCEPLDM_TCK 81 /* RZ/Five Only */ > > > > While NCEPLDM_TCK is listed in the clock list spreadsheet, its > > control bit is not documented. > > > I have got the feedback for the above, NCEPLDM_DM_CLK and NCEPLDM_TCK > clocks cannot be stopped as a result there are no register bits for it > in the HW manual (clock spreadsheet will be updated). I will drop this > and send a v2 including your RB. The question is not if the clocks can be stopped or not, but if there is any need to refer to them from a DT node. What's the nature of the future update to the clock spreadsheet? Of course, if we don't add these clock definitions now, they can still be added later. DT binding definitions are append-only. Thanks! Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, Sorry for the late reply. On Thu, May 19, 2022 at 7:57 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Thu, May 19, 2022 at 7:45 AM Lad, Prabhakar > <prabhakar.csengg@gmail.com> wrote: > > On Tue, May 10, 2022 at 3:02 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > > On Thu, May 5, 2022 at 9:32 PM Lad Prabhakar > > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > > > Renesas RZ/Five SoC has almost the same clock structure compared to the > > > > Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.h header file and just > > > > ammend the RZ/Five CPG clock and reset definitions. > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > > > > --- a/include/dt-bindings/clock/r9a07g043-cpg.h > > > > +++ b/include/dt-bindings/clock/r9a07g043-cpg.h > > > > @@ -108,6 +108,15 @@ > > > > #define R9A07G043_ADC_ADCLK 76 > > > > #define R9A07G043_ADC_PCLK 77 > > > > #define R9A07G043_TSU_PCLK 78 > > > > +#define R9A07G043_NCEPLDM_DM_CLK 79 /* RZ/Five Only */ > > > > > > While NCEPLDM_DM_CLK is listed in the clock list spreadsheet, its > > > control bit is not documented. > > > > > > > +#define R9A07G043_NCEPLDM_ACLK 80 /* RZ/Five Only */ > > > > +#define R9A07G043_NCEPLDM_TCK 81 /* RZ/Five Only */ > > > > > > While NCEPLDM_TCK is listed in the clock list spreadsheet, its > > > control bit is not documented. > > > > > I have got the feedback for the above, NCEPLDM_DM_CLK and NCEPLDM_TCK > > clocks cannot be stopped as a result there are no register bits for it > > in the HW manual (clock spreadsheet will be updated). I will drop this > > and send a v2 including your RB. > > The question is not if the clocks can be stopped or not, but if there > is any need to refer to them from a DT node. As per DT rule we have to add ;) > What's the nature of the future update to the clock spreadsheet? > I have got confirmation from HW team, the UM and clock list will not be updated, * NCEPLDM_DM_CLK, NCEPLDM_TCK and NCEPLDM_ACLK actually exist, and should be listed on the clock list. Only NCEPLDM_ACLK has a mechanism to stop. * Therefore, only NCEPLDM_ACLK should appear on the Clock Control register on the UM. > Of course, if we don't add these clock definitions now, they can > still be added later. DT binding definitions are append-only. > For now I will keep them. Cheers, Prabhakar
diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-bindings/clock/r9a07g043-cpg.h index 27e232733096..77cde8effdc7 100644 --- a/include/dt-bindings/clock/r9a07g043-cpg.h +++ b/include/dt-bindings/clock/r9a07g043-cpg.h @@ -108,6 +108,15 @@ #define R9A07G043_ADC_ADCLK 76 #define R9A07G043_ADC_PCLK 77 #define R9A07G043_TSU_PCLK 78 +#define R9A07G043_NCEPLDM_DM_CLK 79 /* RZ/Five Only */ +#define R9A07G043_NCEPLDM_ACLK 80 /* RZ/Five Only */ +#define R9A07G043_NCEPLDM_TCK 81 /* RZ/Five Only */ +#define R9A07G043_NCEPLMT_ACLK 82 /* RZ/Five Only */ +#define R9A07G043_NCEPLIC_ACLK 83 /* RZ/Five Only */ +#define R9A07G043_AX45MP_CORE0_CLK 84 /* RZ/Five Only */ +#define R9A07G043_AX45MP_ACLK 85 /* RZ/Five Only */ +#define R9A07G043_IAX45_CLK 86 /* RZ/Five Only */ +#define R9A07G043_IAX45_PCLK 87 /* RZ/Five Only */ /* R9A07G043 Resets */ #define R9A07G043_CA55_RST_1_0 0 /* RZ/G2UL Only */ @@ -180,5 +189,16 @@ #define R9A07G043_ADC_PRESETN 67 #define R9A07G043_ADC_ADRST_N 68 #define R9A07G043_TSU_PRESETN 69 +#define R9A07G043_NCEPLDM_DTM_PWR_RST_N 70 /* RZ/Five Only */ +#define R9A07G043_NCEPLDM_ARESETN 71 /* RZ/Five Only */ +#define R9A07G043_NCEPLMT_POR_RSTN 72 /* RZ/Five Only */ +#define R9A07G043_NCEPLMT_ARESETN 73 /* RZ/Five Only */ +#define R9A07G043_NCEPLIC_ARESETN 74 /* RZ/Five Only */ +#define R9A07G043_AX45MP_ARESETNM 75 /* RZ/Five Only */ +#define R9A07G043_AX45MP_ARESETNS 76 /* RZ/Five Only */ +#define R9A07G043_AX45MP_L2_RESETN 77 /* RZ/Five Only */ +#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */ +#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */ + #endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */
Renesas RZ/Five SoC has almost the same clock structure compared to the Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.h header file and just ammend the RZ/Five CPG clock and reset definitions. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- include/dt-bindings/clock/r9a07g043-cpg.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)