| Message ID | 20220620121028.29234-11-rex-bc.chen@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/mediatek: Add MT8195 dp_intf driver | expand |
Hi, Bo-Chen: On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote: > From: Guillaume Ranquet <granquet@baylibre.com> > > dpintf is the displayport interface hardware unit. This unit is > similar > to dpi and can reuse most of the code. > > This patch adds support for mt8195-dpintf to this dpi driver. Main > differences are: > - 4 pixels for one round for dp_intf while dpi is 1 pixel for one > round. > Therefore, pixel clock and timing parameter should be divided by 4 > for > dp_intf. > - Some features/functional components are not available for dpintf > which are now excluded from code execution once is_dpintf is set. > The main difference is some parts of hardware design between > dp_intf > and dpi. > - Some register contents differ slightly between the two components. > To > work around this I added register bits/masks with a DPINTF_ prefix > and use them where different. > > Based on a separate driver for dpintf created by > Jitao shi <jitao.shi@mediatek.com>. > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > [Bo-Chen: Modify reviewers' comments.] > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 65 > +++++++++++++++++++-- > drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 13 +++++ > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 ++ > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 + > 5 files changed, 82 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c > b/drivers/gpu/drm/mediatek/mtk_dpi.c > index e186870ba3bc..2717b1741b7a 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -126,6 +126,7 @@ struct mtk_dpi_conf { > const u32 *output_fmts; > u32 num_output_fmts; > bool is_ck_de_pol; > + bool is_dpintf; > bool swap_input_support; > /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH > (no shift) */ > u32 dimension_mask; > @@ -513,6 +514,14 @@ static int mtk_dpi_set_display_mode(struct > mtk_dpi *dpi, > pll_rate = clk_get_rate(dpi->tvd_clk); > > vm.pixelclock = pll_rate / factor; > + > + /* > + * For dp_intf, we need to divide clock by 4 because it's > + * 4 pixels for one round while dpi is 1 pixel for one round. > + */ > + if (dpi->conf->is_dpintf) > + vm.pixelclock /= 4; I this this should define dpi->conf->round_pixels rather than dpi- >conf->is_dpintf. > + > if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || > (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) > clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); > @@ -534,6 +543,17 @@ static int mtk_dpi_set_display_mode(struct > mtk_dpi *dpi, > hsync.sync_width = vm.hsync_len; > hsync.back_porch = vm.hback_porch; > hsync.front_porch = vm.hfront_porch; > + > + /* > + * For dp_intf, we need to divide everything by 4 because it's > + * 4 pixels for one round while dpi is 1 pixel for one round. > + */ > + if (dpi->conf->is_dpintf) { > + hsync.sync_width = vm.hsync_len / 4; > + hsync.back_porch = vm.hback_porch / 4; > + hsync.front_porch = vm.hfront_porch / 4; > + } Ditto. > + > hsync.shift_half_line = false; > vsync_lodd.sync_width = vm.vsync_len; > vsync_lodd.back_porch = vm.vback_porch; > @@ -575,11 +595,16 @@ static int mtk_dpi_set_display_mode(struct > mtk_dpi *dpi, > mtk_dpi_config_channel_limit(dpi); > mtk_dpi_config_bit_num(dpi, dpi->bit_num); > mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); > - mtk_dpi_config_yc_map(dpi, dpi->yc_map); > mtk_dpi_config_color_format(dpi, dpi->color_format); > - mtk_dpi_config_2n_h_fre(dpi); > - mtk_dpi_dual_edge(dpi); > - mtk_dpi_config_disable_edge(dpi); > + if (dpi->conf->is_dpintf) { Separate this to an independent patch and give a better config name rather than dpi->conf->is_dpintf. > + mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN, > + DPINTF_INPUT_2P_EN); > + } else { > + mtk_dpi_config_yc_map(dpi, dpi->yc_map); > + mtk_dpi_config_2n_h_fre(dpi); > + mtk_dpi_dual_edge(dpi); > + mtk_dpi_config_disable_edge(dpi); > + } > mtk_dpi_sw_reset(dpi, false); > > return 0; > @@ -817,6 +842,16 @@ static unsigned int mt8183_calculate_factor(int > clock) > return 2; > } > [snip] > > #define EDGE_SEL_EN BIT(5) > #define H_FRE_2N BIT(25) > + This seems not related to dpintf support. Regards, CK > #endif /* __MTK_DPI_REGS_H */ >
On Tue, 2022-06-21 at 10:32 +0800, CK Hu wrote: > Hi, Bo-Chen: > > On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote: > > From: Guillaume Ranquet <granquet@baylibre.com> > > > > dpintf is the displayport interface hardware unit. This unit is > > similar > > to dpi and can reuse most of the code. > > > > This patch adds support for mt8195-dpintf to this dpi driver. Main > > differences are: > > - 4 pixels for one round for dp_intf while dpi is 1 pixel for one > > round. > > Therefore, pixel clock and timing parameter should be divided by > > 4 > > for > > dp_intf. > > - Some features/functional components are not available for dpintf > > which are now excluded from code execution once is_dpintf is > > set. > > The main difference is some parts of hardware design between > > dp_intf > > and dpi. > > - Some register contents differ slightly between the two > > components. > > To > > work around this I added register bits/masks with a DPINTF_ > > prefix > > and use them where different. > > > > Based on a separate driver for dpintf created by > > Jitao shi <jitao.shi@mediatek.com>. > > > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > > [Bo-Chen: Modify reviewers' comments.] > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_dpi.c | 65 > > +++++++++++++++++++-- > > drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 13 +++++ > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 ++ > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 + > > 5 files changed, 82 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c > > b/drivers/gpu/drm/mediatek/mtk_dpi.c > > index e186870ba3bc..2717b1741b7a 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > > @@ -126,6 +126,7 @@ struct mtk_dpi_conf { > > const u32 *output_fmts; > > u32 num_output_fmts; > > bool is_ck_de_pol; > > + bool is_dpintf; > > bool swap_input_support; > > /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH > > (no shift) */ > > u32 dimension_mask; > > @@ -513,6 +514,14 @@ static int mtk_dpi_set_display_mode(struct > > mtk_dpi *dpi, > > pll_rate = clk_get_rate(dpi->tvd_clk); > > > > vm.pixelclock = pll_rate / factor; > > + > > + /* > > + * For dp_intf, we need to divide clock by 4 because it's > > + * 4 pixels for one round while dpi is 1 pixel for one round. > > + */ > > + if (dpi->conf->is_dpintf) > > + vm.pixelclock /= 4; > > I this this should define dpi->conf->round_pixels rather than dpi- > > conf->is_dpintf. ok, I will use this config and drop is_dpintf. > > + > > if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || > > (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) > > clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); > > @@ -534,6 +543,17 @@ static int mtk_dpi_set_display_mode(struct > > mtk_dpi *dpi, > > hsync.sync_width = vm.hsync_len; > > hsync.back_porch = vm.hback_porch; > > hsync.front_porch = vm.hfront_porch; > > + > > + /* > > + * For dp_intf, we need to divide everything by 4 because it's > > + * 4 pixels for one round while dpi is 1 pixel for one round. > > + */ > > + if (dpi->conf->is_dpintf) { > > + hsync.sync_width = vm.hsync_len / 4; > > + hsync.back_porch = vm.hback_porch / 4; > > + hsync.front_porch = vm.hfront_porch / 4; > > + } > > Ditto. > > > + > > hsync.shift_half_line = false; > > vsync_lodd.sync_width = vm.vsync_len; > > vsync_lodd.back_porch = vm.vback_porch; > > @@ -575,11 +595,16 @@ static int mtk_dpi_set_display_mode(struct > > mtk_dpi *dpi, > > mtk_dpi_config_channel_limit(dpi); > > mtk_dpi_config_bit_num(dpi, dpi->bit_num); > > mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); > > - mtk_dpi_config_yc_map(dpi, dpi->yc_map); > > mtk_dpi_config_color_format(dpi, dpi->color_format); > > - mtk_dpi_config_2n_h_fre(dpi); > > - mtk_dpi_dual_edge(dpi); > > - mtk_dpi_config_disable_edge(dpi); > > + if (dpi->conf->is_dpintf) { > > Separate this to an independent patch and give a better config name > rather than dpi->conf->is_dpintf. > this is separate config. I will modify like this: add new config "input_2pixel" for input two pixels in this patch: mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN, DPINTF_INPUT_2P_EN); and create another patch to add config "support_direct_pin" this config is only used for dpi which could be directly connect to pins while dp_intf is not. + if (dpi->conf->support_direct_pin) { + mtk_dpi_config_yc_map(dpi, dpi->yc_map); + mtk_dpi_config_2n_h_fre(dpi); + mtk_dpi_dual_edge(dpi); + mtk_dpi_config_disable_edge(dpi); + } BRs, Bo-Chen > > + mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN, > > + DPINTF_INPUT_2P_EN); > > + } else { > > + mtk_dpi_config_yc_map(dpi, dpi->yc_map); > > + mtk_dpi_config_2n_h_fre(dpi); > > + mtk_dpi_dual_edge(dpi); > > + mtk_dpi_config_disable_edge(dpi); > > + } > > mtk_dpi_sw_reset(dpi, false); > > > > return 0; > > @@ -817,6 +842,16 @@ static unsigned int > > mt8183_calculate_factor(int > > clock) > > return 2; > > } > > > > [snip] > > > > > #define EDGE_SEL_EN BIT(5) > > #define H_FRE_2N BIT(25) > > + > > This seems not related to dpintf support. > > Regards, > CK > > > #endif /* __MTK_DPI_REGS_H */ > > > >
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index e186870ba3bc..2717b1741b7a 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -126,6 +126,7 @@ struct mtk_dpi_conf { const u32 *output_fmts; u32 num_output_fmts; bool is_ck_de_pol; + bool is_dpintf; bool swap_input_support; /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) */ u32 dimension_mask; @@ -513,6 +514,14 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, pll_rate = clk_get_rate(dpi->tvd_clk); vm.pixelclock = pll_rate / factor; + + /* + * For dp_intf, we need to divide clock by 4 because it's + * 4 pixels for one round while dpi is 1 pixel for one round. + */ + if (dpi->conf->is_dpintf) + vm.pixelclock /= 4; + if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); @@ -534,6 +543,17 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, hsync.sync_width = vm.hsync_len; hsync.back_porch = vm.hback_porch; hsync.front_porch = vm.hfront_porch; + + /* + * For dp_intf, we need to divide everything by 4 because it's + * 4 pixels for one round while dpi is 1 pixel for one round. + */ + if (dpi->conf->is_dpintf) { + hsync.sync_width = vm.hsync_len / 4; + hsync.back_porch = vm.hback_porch / 4; + hsync.front_porch = vm.hfront_porch / 4; + } + hsync.shift_half_line = false; vsync_lodd.sync_width = vm.vsync_len; vsync_lodd.back_porch = vm.vback_porch; @@ -575,11 +595,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); - mtk_dpi_config_yc_map(dpi, dpi->yc_map); mtk_dpi_config_color_format(dpi, dpi->color_format); - mtk_dpi_config_2n_h_fre(dpi); - mtk_dpi_dual_edge(dpi); - mtk_dpi_config_disable_edge(dpi); + if (dpi->conf->is_dpintf) { + mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN, + DPINTF_INPUT_2P_EN); + } else { + mtk_dpi_config_yc_map(dpi, dpi->yc_map); + mtk_dpi_config_2n_h_fre(dpi); + mtk_dpi_dual_edge(dpi); + mtk_dpi_config_disable_edge(dpi); + } mtk_dpi_sw_reset(dpi, false); return 0; @@ -817,6 +842,16 @@ static unsigned int mt8183_calculate_factor(int clock) return 2; } +static unsigned int mt8195_dpintf_calculate_factor(int clock) +{ + if (clock < 70000) + return 4; + else if (clock < 200000) + return 2; + else + return 1; +} + static const u32 mt8173_output_fmts[] = { MEDIA_BUS_FMT_RGB888_1X24, }; @@ -826,6 +861,12 @@ static const u32 mt8183_output_fmts[] = { MEDIA_BUS_FMT_RGB888_2X12_BE, }; +static const u32 mt8195_output_fmts[] = { + MEDIA_BUS_FMT_RGB888_1X24, + MEDIA_BUS_FMT_YUV8_1X24, + MEDIA_BUS_FMT_YUYV8_1X16, +}; + static const struct mtk_dpi_conf mt8173_conf = { .cal_factor = mt8173_calculate_factor, .reg_h_fre_con = 0xe0, @@ -887,6 +928,19 @@ static const struct mtk_dpi_conf mt8192_conf = { .csc_enable_bit = CSC_ENABLE, }; +static const struct mtk_dpi_conf mt8195_dpintf_conf = { + .cal_factor = mt8195_dpintf_calculate_factor, + .max_clock_khz = 600000, + .output_fmts = mt8195_output_fmts, + .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts), + .is_dpintf = true, + .dimension_mask = DPINTF_HPW_MASK, + .hvsize_mask = DPINTF_HSIZE_MASK, + .channel_swap_shift = DPINTF_CH_SWAP, + .yuv422_en_bit = DPINTF_YUV422_EN, + .csc_enable_bit = DPINTF_CSC_ENABLE, +}; + static int mtk_dpi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1009,6 +1063,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf, }, + { .compatible = "mediatek,mt8195-dp_intf", + .data = &mt8195_dpintf_conf, + }, { }, }; MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h index 3a02fabe1662..f7f0272dbd6a 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -40,9 +40,13 @@ #define FAKE_DE_LEVEN BIT(21) #define FAKE_DE_RODD BIT(22) #define FAKE_DE_REVEN BIT(23) +#define DPINTF_YUV422_EN BIT(24) +#define DPINTF_CSC_ENABLE BIT(26) +#define DPINTF_INPUT_2P_EN BIT(29) #define DPI_OUTPUT_SETTING 0x14 #define CH_SWAP 0 +#define DPINTF_CH_SWAP 1 #define CH_SWAP_MASK (0x7 << 0) #define SWAP_RGB 0x00 #define SWAP_GBR 0x01 @@ -80,8 +84,10 @@ #define DPI_SIZE 0x18 #define HSIZE 0 #define HSIZE_MASK (0x1FFF << 0) +#define DPINTF_HSIZE_MASK (0xFFFF << 0) #define VSIZE 16 #define VSIZE_MASK (0x1FFF << 16) +#define DPINTF_VSIZE_MASK (0xFFFF << 16) #define DPI_DDR_SETTING 0x1C #define DDR_EN BIT(0) @@ -93,24 +99,30 @@ #define DPI_TGEN_HWIDTH 0x20 #define HPW 0 #define HPW_MASK (0xFFF << 0) +#define DPINTF_HPW_MASK (0xFFFF << 0) #define DPI_TGEN_HPORCH 0x24 #define HBP 0 #define HBP_MASK (0xFFF << 0) +#define DPINTF_HBP_MASK (0xFFFF << 0) #define HFP 16 #define HFP_MASK (0xFFF << 16) +#define DPINTF_HFP_MASK (0xFFFF << 16) #define DPI_TGEN_VWIDTH 0x28 #define DPI_TGEN_VPORCH 0x2C #define VSYNC_WIDTH_SHIFT 0 #define VSYNC_WIDTH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_WIDTH_MASK (0xFFFF << 0) #define VSYNC_HALF_LINE_SHIFT 16 #define VSYNC_HALF_LINE_MASK BIT(16) #define VSYNC_BACK_PORCH_SHIFT 0 #define VSYNC_BACK_PORCH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_BACK_PORCH_MASK (0xFFFF << 0) #define VSYNC_FRONT_PORCH_SHIFT 16 #define VSYNC_FRONT_PORCH_MASK (0xFFF << 16) +#define DPINTF_VSYNC_FRONT_PORCH_MASK (0xFFFF << 16) #define DPI_BG_HCNTL 0x30 #define BG_RIGHT (0x1FFF << 0) @@ -217,4 +229,5 @@ #define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25) + #endif /* __MTK_DPI_REGS_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 2aab1e1eda36..5bef085714a1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -427,6 +427,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_RDMA] = "rdma", [MTK_DISP_UFOE] = "ufoe", [MTK_DISP_WDMA] = "wdma", + [MTK_DP_INTF] = "dp-intf", [MTK_DPI] = "dpi", [MTK_DSI] = "dsi", }; @@ -450,6 +451,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX] [DDP_COMPONENT_DRM_OVL_ADAPTOR] = { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_adaptor }, [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc }, [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc }, + [DDP_COMPONENT_DP_INTF0] = { MTK_DP_INTF, 0, &ddp_dpi }, + [DDP_COMPONENT_DP_INTF1] = { MTK_DP_INTF, 1, &ddp_dpi }, [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, @@ -575,6 +578,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, type == MTK_DISP_PWM || type == MTK_DISP_RDMA || type == MTK_DPI || + type == MTK_DP_INTF || type == MTK_DSI) return 0; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index af9a6671f9c4..3084cc4e2830 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -38,6 +38,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DISP_WDMA, MTK_DPI, + MTK_DP_INTF, MTK_DSI, MTK_DDP_COMP_TYPE_MAX, }; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 78e79c8449c8..3b885ad61ac3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -788,6 +788,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt8192-dpi", .data = (void *)MTK_DPI }, + { .compatible = "mediatek,mt8195-dp_intf", + .data = (void *)MTK_DP_INTF }, { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dsi", @@ -931,6 +933,7 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type == MTK_DISP_OVL_2L || comp_type == MTK_DISP_OVL_ADAPTOR || comp_type == MTK_DISP_RDMA || + comp_type == MTK_DP_INTF || comp_type == MTK_DPI || comp_type == MTK_DSI) { dev_info(dev, "Adding component match for %pOF\n",