| Message ID | 20220512104019.19725-1-andrejs.cainikovs@toradex.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | [v1] arm64: dts: imx8mm-verdin: update CAN clock to 40MHz | expand |
On Thu, 2022-05-12 at 12:40 +0200, Andrejs Cainikovs wrote: > Update SPI CAN controller clock to match current hardware design. > > Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> > --- > arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm- > verdin.dtsi > index 0d84d29e70f1..d309bc0ab8f6 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi > @@ -32,10 +32,10 @@ backlight: backlight { > }; > > /* Fixed clock dedicated to SPI CAN controller */ > - clk20m: oscillator { > + clk40m: oscillator { > compatible = "fixed-clock"; > #clock-cells = <0>; > - clock-frequency = <20000000>; > + clock-frequency = <40000000>; > }; > > gpio-keys { > @@ -194,7 +194,7 @@ &ecspi3 { > > can1: can@0 { > compatible = "microchip,mcp251xfd"; > - clocks = <&clk20m>; > + clocks = <&clk40m>; > interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_FALLING>; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_can1_int>;
Hello Shawn, just a ping on this. Francesco On Thu, May 12, 2022 at 12:40:19PM +0200, Andrejs Cainikovs wrote: > Update SPI CAN controller clock to match current hardware design. > > Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com> > --- > arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi > index 0d84d29e70f1..d309bc0ab8f6 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi > @@ -32,10 +32,10 @@ backlight: backlight { > }; > > /* Fixed clock dedicated to SPI CAN controller */ > - clk20m: oscillator { > + clk40m: oscillator { > compatible = "fixed-clock"; > #clock-cells = <0>; > - clock-frequency = <20000000>; > + clock-frequency = <40000000>; > }; > > gpio-keys { > @@ -194,7 +194,7 @@ &ecspi3 { > > can1: can@0 { > compatible = "microchip,mcp251xfd"; > - clocks = <&clk20m>; > + clocks = <&clk40m>; > interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_FALLING>; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_can1_int>; > -- > 2.34.1 >
On 21.06.2022 20:07:49, Francesco Dolcini wrote: > Hello Shawn, just a ping on this. > > Francesco > > On Thu, May 12, 2022 at 12:40:19PM +0200, Andrejs Cainikovs wrote: > > Update SPI CAN controller clock to match current hardware design. > > > > Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com> > > --- > > arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 6 +++--- > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi > > index 0d84d29e70f1..d309bc0ab8f6 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi > > @@ -32,10 +32,10 @@ backlight: backlight { > > }; > > > > /* Fixed clock dedicated to SPI CAN controller */ > > - clk20m: oscillator { > > + clk40m: oscillator { > > compatible = "fixed-clock"; > > #clock-cells = <0>; > > - clock-frequency = <20000000>; > > + clock-frequency = <40000000>; > > }; > > > > gpio-keys { > > @@ -194,7 +194,7 @@ &ecspi3 { > > > > can1: can@0 { > > compatible = "microchip,mcp251xfd"; > > - clocks = <&clk20m>; > > + clocks = <&clk40m>; > > interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_FALLING>; You don't want to use an edge triggered interrupt with the mcp251xfd chip. You will be losing interrupts, better use IRQ_TYPE_LEVEL_LOW. regards, Marc
On Tue, 2022-06-21 at 21:50 +0200, Marc Kleine-Budde wrote: > On 21.06.2022 20:07:49, Francesco Dolcini wrote: > > Hello Shawn, just a ping on this. > > > > Francesco > > > > On Thu, May 12, 2022 at 12:40:19PM +0200, Andrejs Cainikovs wrote: > > > Update SPI CAN controller clock to match current hardware design. > > > > > > Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com> > > > --- > > > arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 6 +++--- > > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi > > > b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi > > > index 0d84d29e70f1..d309bc0ab8f6 100644 > > > --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi > > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi > > > @@ -32,10 +32,10 @@ backlight: backlight { > > > }; > > > > > > /* Fixed clock dedicated to SPI CAN controller */ > > > - clk20m: oscillator { > > > + clk40m: oscillator { > > > compatible = "fixed-clock"; > > > #clock-cells = <0>; > > > - clock-frequency = <20000000>; > > > + clock-frequency = <40000000>; > > > }; > > > > > > gpio-keys { > > > @@ -194,7 +194,7 @@ &ecspi3 { > > > > > > can1: can@0 { > > > compatible = "microchip,mcp251xfd"; > > > - clocks = <&clk20m>; > > > + clocks = <&clk40m>; > > > interrupts-extended = <&gpio1 6 > > > IRQ_TYPE_EDGE_FALLING>; > > You don't want to use an edge triggered interrupt with the mcp251xfd > chip. You will be losing interrupts, better use IRQ_TYPE_LEVEL_LOW. > > regards, > Marc > Hi Marc, This particular change is not about interrupts. But thanks for a hint, I'll make sure this is addressed. Best regards, Andrejs Cainikovs.
On 22.06.2022 08:38:04, Andrejs Cainikovs wrote: > > > > can1: can@0 { > > > > compatible = "microchip,mcp251xfd"; > > > > - clocks = <&clk20m>; > > > > + clocks = <&clk40m>; > > > > interrupts-extended = <&gpio1 6 > > > > IRQ_TYPE_EDGE_FALLING>; > > > > You don't want to use an edge triggered interrupt with the mcp251xfd > > chip. You will be losing interrupts, better use IRQ_TYPE_LEVEL_LOW. > > This particular change is not about interrupts. Sure, I just noticed it. > But thanks for a hint, I'll make sure this is addressed. Thanks, Marc
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 0d84d29e70f1..d309bc0ab8f6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -32,10 +32,10 @@ backlight: backlight { }; /* Fixed clock dedicated to SPI CAN controller */ - clk20m: oscillator { + clk40m: oscillator { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <20000000>; + clock-frequency = <40000000>; }; gpio-keys { @@ -194,7 +194,7 @@ &ecspi3 { can1: can@0 { compatible = "microchip,mcp251xfd"; - clocks = <&clk20m>; + clocks = <&clk40m>; interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_int>;
Update SPI CAN controller clock to match current hardware design. Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com> --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)