| Message ID | 20220625074422.3479591-3-haijie1@huawei.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | dmaengine: hisilicon: Add support for hisi dma driver | expand |
Hi Jie,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on vkoul-dmaengine/next]
[also build test ERROR on linus/master v5.19-rc3 next-20220624]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Jie-Hai/dmaengine-hisilicon-Add-support-for-hisi-dma-driver/20220625-154524
base: https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git next
config: arc-allyesconfig
compiler: arceb-elf-gcc (GCC) 11.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/4a79d13d35e4f95c88bc0dfb44923dbd030bb126
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jie-Hai/dmaengine-hisilicon-Add-support-for-hisi-dma-driver/20220625-154524
git checkout 4a79d13d35e4f95c88bc0dfb44923dbd030bb126
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.3.0 make.cross W=1 O=build_dir ARCH=arc SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>
Note: the linux-review/Jie-Hai/dmaengine-hisilicon-Add-support-for-hisi-dma-driver/20220625-154524 HEAD e823cc5940ad1d20993113591a7ba26946ae0840 builds fine.
It only hurts bisectability.
All errors (new ones prefixed by >>):
drivers/dma/hisi_dma.c: In function 'hisi_dma_irq':
>> drivers/dma/hisi_dma.c:441:37: error: 'q_base' undeclared (first use in this function)
441 | hisi_dma_chan_write(q_base, HISI_DMA_Q_CQ_HEAD_PTR,
| ^~~~~~
drivers/dma/hisi_dma.c:441:37: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/dma/hisi_dma.c:441:45: error: 'HISI_DMA_Q_CQ_HEAD_PTR' undeclared (first use in this function); did you mean 'HISI_DMA_CQ_HEAD_PTR'?
441 | hisi_dma_chan_write(q_base, HISI_DMA_Q_CQ_HEAD_PTR,
| ^~~~~~~~~~~~~~~~~~~~~~
| HISI_DMA_CQ_HEAD_PTR
vim +/q_base +441 drivers/dma/hisi_dma.c
426
427 static irqreturn_t hisi_dma_irq(int irq, void *data)
428 {
429 struct hisi_dma_chan *chan = data;
430 struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
431 struct hisi_dma_desc *desc;
432 struct hisi_dma_cqe *cqe;
433
434 spin_lock(&chan->vc.lock);
435
436 desc = chan->desc;
437 cqe = chan->cq + chan->cq_head;
438 if (desc) {
439 chan->cq_head = (chan->cq_head + 1) %
440 hdma_dev->chan_depth;
> 441 hisi_dma_chan_write(q_base, HISI_DMA_Q_CQ_HEAD_PTR,
442 chan->qp_num, chan->cq_head);
443 if (FIELD_GET(STATUS_MASK, cqe->w0) == STATUS_SUCC) {
444 vchan_cookie_complete(&desc->vd);
445 } else {
446 dev_err(&hdma_dev->pdev->dev, "task error!\n");
447 }
448
449 chan->desc = NULL;
450 }
451
452 spin_unlock(&chan->vc.lock);
453
454 return IRQ_HANDLED;
455 }
456
On 25-06-22, 15:44, Jie Hai wrote: > After completion of data transfer of one or multiple descriptors, > the completion status and the current head pointer to submission > queue are written into the CQ and interrupt can be generated to > inform the software. In interrupt process CQ is read and cq_head > is updated. > > hisi_dma_irq updates cq_head only when the completion status is > success. When an abnormal interrupt reports, cq_head will not update > which will cause subsequent interrupt processes read the error CQ > and never report the correct status. > > This patch updates cq_head whenever CQ is accessed. > > Fixes: e9f08b65250d ("dmaengine: hisilicon: Add Kunpeng DMA engine support") > No need for blank line > Signed-off-by: Jie Hai <haijie1@huawei.com> > --- > drivers/dma/hisi_dma.c | 9 ++++----- > 1 file changed, 4 insertions(+), 5 deletions(-) > > diff --git a/drivers/dma/hisi_dma.c b/drivers/dma/hisi_dma.c > index 98bc488893cc..0a0f8a4d168a 100644 > --- a/drivers/dma/hisi_dma.c > +++ b/drivers/dma/hisi_dma.c > @@ -436,12 +436,11 @@ static irqreturn_t hisi_dma_irq(int irq, void *data) > desc = chan->desc; > cqe = chan->cq + chan->cq_head; > if (desc) { > + chan->cq_head = (chan->cq_head + 1) % > + hdma_dev->chan_depth; > + hisi_dma_chan_write(q_base, HISI_DMA_Q_CQ_HEAD_PTR, q_base?
Hi, kernel test robot, Thanks and this will be corrected in the next version. -----Original Message----- From: kernel test robot [mailto:lkp@intel.com] Sent: Sunday, June 26, 2022 9:38 PM To: haijie <haijie1@huawei.com>; vkoul@kernel.org; Wangzhou (B) <wangzhou1@hisilicon.com> Cc: kbuild-all@lists.01.org; dmaengine@vger.kernel.org; linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/8] dmaengine: hisilicon: Fix CQ head update Hi Jie, Thank you for the patch! Yet something to improve: [auto build test ERROR on vkoul-dmaengine/next] [also build test ERROR on linus/master v5.19-rc3 next-20220624] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/intel-lab-lkp/linux/commits/Jie-Hai/dmaengine-hisilicon-Add-support-for-hisi-dma-driver/20220625-154524 base: https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git next config: arc-allyesconfig compiler: arceb-elf-gcc (GCC) 11.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/intel-lab-lkp/linux/commit/4a79d13d35e4f95c88bc0dfb44923dbd030bb126 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Jie-Hai/dmaengine-hisilicon-Add-support-for-hisi-dma-driver/20220625-154524 git checkout 4a79d13d35e4f95c88bc0dfb44923dbd030bb126 # save the config file mkdir build_dir && cp config build_dir/.config COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.3.0 make.cross W=1 O=build_dir ARCH=arc SHELL=/bin/bash If you fix the issue, kindly add following tag where applicable Reported-by: kernel test robot <lkp@intel.com> Note: the linux-review/Jie-Hai/dmaengine-hisilicon-Add-support-for-hisi-dma-driver/20220625-154524 HEAD e823cc5940ad1d20993113591a7ba26946ae0840 builds fine. It only hurts bisectability. All errors (new ones prefixed by >>): drivers/dma/hisi_dma.c: In function 'hisi_dma_irq': >> drivers/dma/hisi_dma.c:441:37: error: 'q_base' undeclared (first use >> in this function) 441 | hisi_dma_chan_write(q_base, HISI_DMA_Q_CQ_HEAD_PTR, | ^~~~~~ drivers/dma/hisi_dma.c:441:37: note: each undeclared identifier is reported only once for each function it appears in >> drivers/dma/hisi_dma.c:441:45: error: 'HISI_DMA_Q_CQ_HEAD_PTR' undeclared (first use in this function); did you mean 'HISI_DMA_CQ_HEAD_PTR'? 441 | hisi_dma_chan_write(q_base, HISI_DMA_Q_CQ_HEAD_PTR, | ^~~~~~~~~~~~~~~~~~~~~~ | HISI_DMA_CQ_HEAD_PTR vim +/q_base +441 drivers/dma/hisi_dma.c 426 427 static irqreturn_t hisi_dma_irq(int irq, void *data) 428 { 429 struct hisi_dma_chan *chan = data; 430 struct hisi_dma_dev *hdma_dev = chan->hdma_dev; 431 struct hisi_dma_desc *desc; 432 struct hisi_dma_cqe *cqe; 433 434 spin_lock(&chan->vc.lock); 435 436 desc = chan->desc; 437 cqe = chan->cq + chan->cq_head; 438 if (desc) { 439 chan->cq_head = (chan->cq_head + 1) % 440 hdma_dev->chan_depth; > 441 hisi_dma_chan_write(q_base, HISI_DMA_Q_CQ_HEAD_PTR, 442 chan->qp_num, chan->cq_head); 443 if (FIELD_GET(STATUS_MASK, cqe->w0) == STATUS_SUCC) { 444 vchan_cookie_complete(&desc->vd); 445 } else { 446 dev_err(&hdma_dev->pdev->dev, "task error!\n"); 447 } 448 449 chan->desc = NULL; 450 } 451 452 spin_unlock(&chan->vc.lock); 453 454 return IRQ_HANDLED; 455 } 456 -- 0-DAY CI Kernel Test Service https://01.org/lkp
Hi, Vinod, This happens bacause I rearranged this patch without checking, it will be corrected in v2. Thanks. -----Original Message----- From: Vinod Koul [mailto:vkoul@kernel.org] Sent: Monday, June 27, 2022 2:13 PM To: haijie <haijie1@huawei.com> Cc: Wangzhou (B) <wangzhou1@hisilicon.com>; dmaengine@vger.kernel.org; linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/8] dmaengine: hisilicon: Fix CQ head update On 25-06-22, 15:44, Jie Hai wrote: > After completion of data transfer of one or multiple descriptors, the > completion status and the current head pointer to submission queue are > written into the CQ and interrupt can be generated to inform the > software. In interrupt process CQ is read and cq_head is updated. > > hisi_dma_irq updates cq_head only when the completion status is > success. When an abnormal interrupt reports, cq_head will not update > which will cause subsequent interrupt processes read the error CQ and > never report the correct status. > > This patch updates cq_head whenever CQ is accessed. > > Fixes: e9f08b65250d ("dmaengine: hisilicon: Add Kunpeng DMA engine > support") > No need for blank line > Signed-off-by: Jie Hai <haijie1@huawei.com> > --- > drivers/dma/hisi_dma.c | 9 ++++----- > 1 file changed, 4 insertions(+), 5 deletions(-) > > diff --git a/drivers/dma/hisi_dma.c b/drivers/dma/hisi_dma.c index > 98bc488893cc..0a0f8a4d168a 100644 > --- a/drivers/dma/hisi_dma.c > +++ b/drivers/dma/hisi_dma.c > @@ -436,12 +436,11 @@ static irqreturn_t hisi_dma_irq(int irq, void *data) > desc = chan->desc; > cqe = chan->cq + chan->cq_head; > if (desc) { > + chan->cq_head = (chan->cq_head + 1) % > + hdma_dev->chan_depth; > + hisi_dma_chan_write(q_base, HISI_DMA_Q_CQ_HEAD_PTR, q_base? -- ~Vinod
On 27-06-22, 07:01, haijie wrote: > Hi, Vinod, > > This happens bacause I rearranged this patch without checking, it will be corrected in v2. Please _do_ _not_ top post and reply inline to the queries. Otherwise it is very difficult to understand... > > Thanks. > > -----Original Message----- > From: Vinod Koul [mailto:vkoul@kernel.org] > Sent: Monday, June 27, 2022 2:13 PM > To: haijie <haijie1@huawei.com> > Cc: Wangzhou (B) <wangzhou1@hisilicon.com>; dmaengine@vger.kernel.org; linux-kernel@vger.kernel.org > Subject: Re: [PATCH 2/8] dmaengine: hisilicon: Fix CQ head update > > On 25-06-22, 15:44, Jie Hai wrote: > > After completion of data transfer of one or multiple descriptors, the > > completion status and the current head pointer to submission queue are > > written into the CQ and interrupt can be generated to inform the > > software. In interrupt process CQ is read and cq_head is updated. > > > > hisi_dma_irq updates cq_head only when the completion status is > > success. When an abnormal interrupt reports, cq_head will not update > > which will cause subsequent interrupt processes read the error CQ and > > never report the correct status. > > > > This patch updates cq_head whenever CQ is accessed. > > > > Fixes: e9f08b65250d ("dmaengine: hisilicon: Add Kunpeng DMA engine > > support") > > > > No need for blank line > > Signed-off-by: Jie Hai <haijie1@huawei.com> > > --- > > drivers/dma/hisi_dma.c | 9 ++++----- > > 1 file changed, 4 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/dma/hisi_dma.c b/drivers/dma/hisi_dma.c index > > 98bc488893cc..0a0f8a4d168a 100644 > > --- a/drivers/dma/hisi_dma.c > > +++ b/drivers/dma/hisi_dma.c > > @@ -436,12 +436,11 @@ static irqreturn_t hisi_dma_irq(int irq, void *data) > > desc = chan->desc; > > cqe = chan->cq + chan->cq_head; > > if (desc) { > > + chan->cq_head = (chan->cq_head + 1) % > > + hdma_dev->chan_depth; > > + hisi_dma_chan_write(q_base, HISI_DMA_Q_CQ_HEAD_PTR, > > q_base? > > -- > ~Vinod
diff --git a/drivers/dma/hisi_dma.c b/drivers/dma/hisi_dma.c index 98bc488893cc..0a0f8a4d168a 100644 --- a/drivers/dma/hisi_dma.c +++ b/drivers/dma/hisi_dma.c @@ -436,12 +436,11 @@ static irqreturn_t hisi_dma_irq(int irq, void *data) desc = chan->desc; cqe = chan->cq + chan->cq_head; if (desc) { + chan->cq_head = (chan->cq_head + 1) % + hdma_dev->chan_depth; + hisi_dma_chan_write(q_base, HISI_DMA_Q_CQ_HEAD_PTR, + chan->qp_num, chan->cq_head); if (FIELD_GET(STATUS_MASK, cqe->w0) == STATUS_SUCC) { - chan->cq_head = (chan->cq_head + 1) % - hdma_dev->chan_depth; - hisi_dma_chan_write(hdma_dev->base, - HISI_DMA_CQ_HEAD_PTR, chan->qp_num, - chan->cq_head); vchan_cookie_complete(&desc->vd); } else { dev_err(&hdma_dev->pdev->dev, "task error!\n");
After completion of data transfer of one or multiple descriptors, the completion status and the current head pointer to submission queue are written into the CQ and interrupt can be generated to inform the software. In interrupt process CQ is read and cq_head is updated. hisi_dma_irq updates cq_head only when the completion status is success. When an abnormal interrupt reports, cq_head will not update which will cause subsequent interrupt processes read the error CQ and never report the correct status. This patch updates cq_head whenever CQ is accessed. Fixes: e9f08b65250d ("dmaengine: hisilicon: Add Kunpeng DMA engine support") Signed-off-by: Jie Hai <haijie1@huawei.com> --- drivers/dma/hisi_dma.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-)