[v5,1/4] dt-bindings: interconnect: qcom,msm8998-cpu-bwmon: add BWMON device

Commit Message

Krzysztof Kozlowski June 29, 2022, 7:52 a.m. UTC

Add bindings for the Qualcomm Bandwidth Monitor device providing
performance data on interconnects.  The bindings describe only BWMON CPU
(version 4), e.g. the instance which appeared for the first on Qualcomm
MSM8998 SoC and is also used on SDM845.  This BWMON device sits between
CPU and Last Level Cache Controller.

Signed-off-by: Krzysztof Kozlowski <[e-mail]>
Reviewed-by: Rob Herring <[e-mail]>
Acked-by: Georgi Djakov <[e-mail]>
---
 .../interconnect/qcom,msm8998-cpu-bwmon.yaml  | 80 +++++++++++++++++++
 1 file changed, 80 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,msm8998-cpu-bwmon.yaml

Comments

Rajendra Nayak June 29, 2022, 11:21 a.m. UTC | #1

> This BWMON device sits between
> CPU and Last Level Cache Controller.

[]...

> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - enum:
> +              - qcom,sdm845-cpu-bwmon

should this be qcom,sdm845-llcc-bwmon instead since it actually
tells us the llcc bw values?
That way perhaps the other one between llcc and DDR can be
qcom,sdm845-ddr-bwmon.

> +          - const: qcom,msm8998-cpu-bwmon
> +      - const: qcom,msm8998-cpu-bwmon       # BWMON v4
> +

Krzysztof Kozlowski June 29, 2022, 11:22 a.m. UTC | #2

On 29/06/2022 13:21, Rajendra Nayak wrote:
> 
>> This BWMON device sits between
>> CPU and Last Level Cache Controller.
> 
> []...
> 
>> +properties:
>> +  compatible:
>> +    oneOf:
>> +      - items:
>> +          - enum:
>> +              - qcom,sdm845-cpu-bwmon
> 
> should this be qcom,sdm845-llcc-bwmon instead since it actually
> tells us the llcc bw values?
> That way perhaps the other one between llcc and DDR can be
> qcom,sdm845-ddr-bwmon.
> 

Good point, thanks. I'll change it.

Best regards,
Krzysztof

Bjorn Andersson June 30, 2022, 2:26 p.m. UTC | #3

On Wed 29 Jun 06:21 CDT 2022, Rajendra Nayak wrote:

> 
> > This BWMON device sits between
> > CPU and Last Level Cache Controller.
> 
> []...
> 
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - enum:
> > +              - qcom,sdm845-cpu-bwmon
> 
> should this be qcom,sdm845-llcc-bwmon instead since it actually
> tells us the llcc bw values?
> That way perhaps the other one between llcc and DDR can be
> qcom,sdm845-ddr-bwmon.
> 

My understanding is that this bwmon instance measures the data
throughput on the CPU subsystem-ports and that the bwmon5 instance
measures the traffic from the memnoc towards LLCC and DDR.

Which matches the downstream naming of bwmon4 == cpu, bwmon5 == llcc.

Regards,
Bjorn

Patch

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-cpu-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-cpu-bwmon.yaml
new file mode 100644
index 000000000000..b6ced53b92f7
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-cpu-bwmon.yaml
@@ -0,0 +1,80 @@ 
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,msm8998-cpu-bwmon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Interconnect Bandwidth Monitor
+
+maintainers:
+  - Krzysztof Kozlowski <[e-mail]>
+
+description:
+  Bandwidth Monitor measures current throughput on buses between various NoC
+  fabrics and provides information when it crosses configured thresholds.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - qcom,sdm845-cpu-bwmon
+          - const: qcom,msm8998-cpu-bwmon
+      - const: qcom,msm8998-cpu-bwmon       # BWMON v4
+
+  interconnects:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  operating-points-v2: true
+  opp-table: true
+
+  reg:
+    # Currently described BWMON v4 and v5 use one register address space.
+    # BWMON v2 uses two register spaces - not yet described.
+    maxItems: 1
+
+required:
+  - compatible
+  - interconnects
+  - interrupts
+  - operating-points-v2
+  - opp-table
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interconnect/qcom,sdm845.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    pmu@1436400 {
+        compatible = "qcom,sdm845-cpu-bwmon", "qcom,msm8998-cpu-bwmon";
+        reg = <0x01436400 0x600>;
+        interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+        interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
+
+        operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+        cpu_bwmon_opp_table: opp-table {
+            compatible = "operating-points-v2";
+            opp-0 {
+                opp-peak-kBps = <4800000>;
+            };
+            opp-1 {
+                opp-peak-kBps = <9216000>;
+            };
+            opp-2 {
+                opp-peak-kBps = <15052800>;
+            };
+            opp-3 {
+                opp-peak-kBps = <20889600>;
+            };
+            opp-4 {
+                opp-peak-kBps = <25497600>;
+            };
+        };
+    };