| Message ID | 20220701065634.4027537-2-victor.liu@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/bridge: fsl-ldb: A few fixes | expand |
On 7/1/22 08:56, Liu Ying wrote: > With LVDS dual link, up to 160MHz mode clock rate is supported. > With LVDS single link, up to 80MHz mode clock rate is supported. > Fix mode clock rate validation by swapping the maximum mode clock > rates of the two link modes. > > Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB bridge") > Cc: Andrzej Hajda <andrzej.hajda@intel.com> > Cc: Neil Armstrong <narmstrong@baylibre.com> > Cc: Robert Foss <robert.foss@linaro.org> > Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> > Cc: Jonas Karlman <jonas@kwiboo.se> > Cc: Jernej Skrabec <jernej.skrabec@gmail.com> > Cc: David Airlie <airlied@linux.ie> > Cc: Daniel Vetter <daniel@ffwll.ch> > Cc: Sam Ravnborg <sam@ravnborg.org> > Cc: Marek Vasut <marex@denx.de> > Cc: NXP Linux Team <linux-imx@nxp.com> > Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Marek Vasut <marex@denx.de>
On Fri, 1 Jul 2022 at 13:00, Marek Vasut <marex@denx.de> wrote: > > On 7/1/22 08:56, Liu Ying wrote: > > With LVDS dual link, up to 160MHz mode clock rate is supported. > > With LVDS single link, up to 80MHz mode clock rate is supported. > > Fix mode clock rate validation by swapping the maximum mode clock > > rates of the two link modes. > > > > Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB bridge") > > Cc: Andrzej Hajda <andrzej.hajda@intel.com> > > Cc: Neil Armstrong <narmstrong@baylibre.com> > > Cc: Robert Foss <robert.foss@linaro.org> > > Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> > > Cc: Jonas Karlman <jonas@kwiboo.se> > > Cc: Jernej Skrabec <jernej.skrabec@gmail.com> > > Cc: David Airlie <airlied@linux.ie> > > Cc: Daniel Vetter <daniel@ffwll.ch> > > Cc: Sam Ravnborg <sam@ravnborg.org> > > Cc: Marek Vasut <marex@denx.de> > > Cc: NXP Linux Team <linux-imx@nxp.com> > > Signed-off-by: Liu Ying <victor.liu@nxp.com> > > Reviewed-by: Marek Vasut <marex@denx.de> Applied 1-2/3 to drm-misc-next. Picked Mareks patch for 3/3 since it was submitted first and is identical.
Hi, On 06/07/2022 15:34, Robert Foss wrote: > On Fri, 1 Jul 2022 at 13:00, Marek Vasut <marex@denx.de> wrote: >> >> On 7/1/22 08:56, Liu Ying wrote: >>> With LVDS dual link, up to 160MHz mode clock rate is supported. >>> With LVDS single link, up to 80MHz mode clock rate is supported. >>> Fix mode clock rate validation by swapping the maximum mode clock >>> rates of the two link modes. >>> >>> Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB bridge") >>> Cc: Andrzej Hajda <andrzej.hajda@intel.com> >>> Cc: Neil Armstrong <narmstrong@baylibre.com> >>> Cc: Robert Foss <robert.foss@linaro.org> >>> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> >>> Cc: Jonas Karlman <jonas@kwiboo.se> >>> Cc: Jernej Skrabec <jernej.skrabec@gmail.com> >>> Cc: David Airlie <airlied@linux.ie> >>> Cc: Daniel Vetter <daniel@ffwll.ch> >>> Cc: Sam Ravnborg <sam@ravnborg.org> >>> Cc: Marek Vasut <marex@denx.de> >>> Cc: NXP Linux Team <linux-imx@nxp.com> >>> Signed-off-by: Liu Ying <victor.liu@nxp.com> >> >> Reviewed-by: Marek Vasut <marex@denx.de> > > Applied 1-2/3 to drm-misc-next. Picked Mareks patch for 3/3 since it > was submitted first and is identical. Seems we'll have a conflict when drm-misc-fixes is backmerged in drm-misc-next ! Neil
diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c index b2675c769a55..3cb3b310e283 100644 --- a/drivers/gpu/drm/bridge/fsl-ldb.c +++ b/drivers/gpu/drm/bridge/fsl-ldb.c @@ -233,7 +233,7 @@ fsl_ldb_mode_valid(struct drm_bridge *bridge, { struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); - if (mode->clock > (fsl_ldb->lvds_dual_link ? 80000 : 160000)) + if (mode->clock > (fsl_ldb->lvds_dual_link ? 160000 : 80000)) return MODE_CLOCK_HIGH; return MODE_OK;
With LVDS dual link, up to 160MHz mode clock rate is supported. With LVDS single link, up to 80MHz mode clock rate is supported. Fix mode clock rate validation by swapping the maximum mode clock rates of the two link modes. Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB bridge") Cc: Andrzej Hajda <andrzej.hajda@intel.com> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Robert Foss <robert.foss@linaro.org> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> Cc: Jonas Karlman <jonas@kwiboo.se> Cc: Jernej Skrabec <jernej.skrabec@gmail.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Marek Vasut <marex@denx.de> Cc: NXP Linux Team <linux-imx@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> --- drivers/gpu/drm/bridge/fsl-ldb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)