| Message ID | 20220706110619.71729-3-kavyasree.kotagiri@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for lan966x flexcom chip-select configuration | expand |
On Wed, Jul 06, 2022 at 09:06:18AM -0200, Kavyasree Kotagiri wrote: > LAN966x SoC flexcoms has two optional I/O lines. Namely, CS0 and CS1 > in flexcom SPI mode. CTS and RTS in flexcom USART mode. These pins > can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage depends on > functions being configured. > > Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> > --- > v6 -> v7: > - Add #address-cells, #size-cells to flx3 example. > > v5 -> v6: > - Removed spi node from flx3 example. > > v4 -> v5: > - Fixed indentations and dt-schema errors. > - No errors seen with 'make dt_binding_check'. > > v3 -> v4: > - Added else condition to allOf:if:then. > > v2 -> v3: > - Add reg property of lan966x missed in v2. > > v1 -> v2: > - Use allOf:if:then for lan966x dt properties > > .../bindings/mfd/atmel,sama5d2-flexcom.yaml | 65 ++++++++++++++++++- > 1 file changed, 64 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml > index 864f490ffb83..b4b47accab49 100644 > --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml > +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml > @@ -18,9 +18,11 @@ properties: > compatible: > enum: > - atmel,sama5d2-flexcom > + - microchip,lan966x-flexcom Don't use wildcards in compatible strings. > > reg: > - maxItems: 1 > + minItems: 1 > + maxItems: 2 > > clocks: > maxItems: 1 > @@ -47,6 +49,27 @@ properties: > $ref: /schemas/types.yaml#/definitions/uint32 > enum: [1, 2, 3] > > + microchip,flx-shrd-pins: > + description: Specify the Flexcom shared pins to be used for flexcom > + chip-selects. > + $ref: /schemas/types.yaml#/definitions/uint32-array > + minItems: 1 > + maxItems: 2 > + items: > + minimum: 0 > + maximum: 20 It's not clear how one uses this. It's selecting 2 pins, or a range of pins, or ??? > + > + microchip,flx-cs: > + description: Flexcom chip selects. Here, value of '0' represents "cts" line > + of flexcom USART or "cs0" line of flexcom SPI and value of '1' represents > + "rts" line of flexcom USART or "cs1" line of flexcom SPI. > + $ref: /schemas/types.yaml#/definitions/uint32-array > + minItems: 1 > + maxItems: 2 > + items: > + minimum: 0 > + maximum: 1 > + > required: > - compatible > - reg > @@ -56,6 +79,31 @@ required: > - ranges > - atmel,flexcom-mode > > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: microchip,lan966x-flexcom > + > + then: > + properties: > + reg: > + items: > + - description: Flexcom base registers map > + - description: Flexcom shared registers map > + required: > + - microchip,flx-shrd-pins > + - microchip,flx-cs > + > + else: > + properties: > + reg: > + items: > + - description: Flexcom base registers map > + microchip,flx-shrd-pins: false > + microchip,flx-cs: false > + > additionalProperties: false > > examples: > @@ -71,4 +119,19 @@ examples: > ranges = <0x0 0xf8034000 0x800>; > atmel,flexcom-mode = <2>; > }; > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + flx3: flexcom@e0064000 { > + compatible = "microchip,lan966x-flexcom"; > + reg = <0xe0064000 0x100>, > + <0xe2004180 0x8>; > + clocks = <&flx0_clk>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0xe0040000 0x800>; > + atmel,flexcom-mode = <2>; > + microchip,flx-shrd-pins = <9>; > + microchip,flx-cs = <0>; > + }; > ... > -- > 2.25.1 > >
> > @@ -18,9 +18,11 @@ properties: > > compatible: > > enum: > > - atmel,sama5d2-flexcom > > + - microchip,lan966x-flexcom > > Don't use wildcards in compatible strings. > Ok. I will change it. > > > > reg: > > - maxItems: 1 > > + minItems: 1 > > + maxItems: 2 > > > > clocks: > > maxItems: 1 > > @@ -47,6 +49,27 @@ properties: > > $ref: /schemas/types.yaml#/definitions/uint32 > > enum: [1, 2, 3] > > > > + microchip,flx-shrd-pins: > > + description: Specify the Flexcom shared pins to be used for flexcom > > + chip-selects. > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > + minItems: 1 > > + maxItems: 2 > > + items: > > + minimum: 0 > > + maximum: 20 > > It's not clear how one uses this. It's selecting 2 pins, or a range of > pins, or ??? > I used minItems and maxItems to represent number of entries allowed. Either one shared pin can be mapped or max of 2 based on pins mapped on board and 0-20 is allowed shared pin numbers. > > + > > + microchip,flx-cs: > > + description: Flexcom chip selects. Here, value of '0' represents "cts" line > > + of flexcom USART or "cs0" line of flexcom SPI and value of '1' > represents > > + "rts" line of flexcom USART or "cs1" line of flexcom SPI. > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > + minItems: 1 > > + maxItems: 2 > > + items: > > + minimum: 0 > > + maximum: 1 > > + > > required: > > - compatible > > - reg > > @@ -56,6 +79,31 @@ required: > > - ranges > > - atmel,flexcom-mode > > > > +allOf: > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: microchip,lan966x-flexcom > > + > > + then: > > + properties: > > + reg: > > + items: > > + - description: Flexcom base registers map > > + - description: Flexcom shared registers map > > + required: > > + - microchip,flx-shrd-pins > > + - microchip,flx-cs > > + > > + else: > > + properties: > > + reg: > > + items: > > + - description: Flexcom base registers map > > + microchip,flx-shrd-pins: false > > + microchip,flx-cs: false > > + > > additionalProperties: false > > > > examples: > > @@ -71,4 +119,19 @@ examples: > > ranges = <0x0 0xf8034000 0x800>; > > atmel,flexcom-mode = <2>; > > }; > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + > > + flx3: flexcom@e0064000 { > > + compatible = "microchip,lan966x-flexcom"; > > + reg = <0xe0064000 0x100>, > > + <0xe2004180 0x8>; > > + clocks = <&flx0_clk>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0x0 0xe0040000 0x800>; > > + atmel,flexcom-mode = <2>; > > + microchip,flx-shrd-pins = <9>; > > + microchip,flx-cs = <0>; > > + }; > > ... > > -- > > 2.25.1 > > > >
diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml index 864f490ffb83..b4b47accab49 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -18,9 +18,11 @@ properties: compatible: enum: - atmel,sama5d2-flexcom + - microchip,lan966x-flexcom reg: - maxItems: 1 + minItems: 1 + maxItems: 2 clocks: maxItems: 1 @@ -47,6 +49,27 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [1, 2, 3] + microchip,flx-shrd-pins: + description: Specify the Flexcom shared pins to be used for flexcom + chip-selects. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 20 + + microchip,flx-cs: + description: Flexcom chip selects. Here, value of '0' represents "cts" line + of flexcom USART or "cs0" line of flexcom SPI and value of '1' represents + "rts" line of flexcom USART or "cs1" line of flexcom SPI. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 1 + required: - compatible - reg @@ -56,6 +79,31 @@ required: - ranges - atmel,flexcom-mode +allOf: + - if: + properties: + compatible: + contains: + const: microchip,lan966x-flexcom + + then: + properties: + reg: + items: + - description: Flexcom base registers map + - description: Flexcom shared registers map + required: + - microchip,flx-shrd-pins + - microchip,flx-cs + + else: + properties: + reg: + items: + - description: Flexcom base registers map + microchip,flx-shrd-pins: false + microchip,flx-cs: false + additionalProperties: false examples: @@ -71,4 +119,19 @@ examples: ranges = <0x0 0xf8034000 0x800>; atmel,flexcom-mode = <2>; }; + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + flx3: flexcom@e0064000 { + compatible = "microchip,lan966x-flexcom"; + reg = <0xe0064000 0x100>, + <0xe2004180 0x8>; + clocks = <&flx0_clk>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0040000 0x800>; + atmel,flexcom-mode = <2>; + microchip,flx-shrd-pins = <9>; + microchip,flx-cs = <0>; + }; ...
LAN966x SoC flexcoms has two optional I/O lines. Namely, CS0 and CS1 in flexcom SPI mode. CTS and RTS in flexcom USART mode. These pins can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage depends on functions being configured. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> --- v6 -> v7: - Add #address-cells, #size-cells to flx3 example. v5 -> v6: - Removed spi node from flx3 example. v4 -> v5: - Fixed indentations and dt-schema errors. - No errors seen with 'make dt_binding_check'. v3 -> v4: - Added else condition to allOf:if:then. v2 -> v3: - Add reg property of lan966x missed in v2. v1 -> v2: - Use allOf:if:then for lan966x dt properties .../bindings/mfd/atmel,sama5d2-flexcom.yaml | 65 ++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-)