| Message ID | 1656055682-18817-1-git-send-email-quic_krichai@quicinc.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | PCI: Restrict pci transactions after pci suspend | expand |
If the endpoint device state is D0 and irq's are not freed, then kernel try to mask interrupts by writing in to the vector table (for MSIX interrupts) and config space (for MSI's). These transactions are initiated after clocks are getting disabled as part of PM suspend call. Due to it, these transactions are resulting in un-clocked access and eventual to crashes. So added a logic in qcom driver to restrict the unclocked access. And updated the logic to check the link state before masking or unmasking the interrupts. Krishna chaitanya chundru (2): PCI: qcom: Add system PM support PCI: qcom: Restrict pci transactions after pci suspend drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++- drivers/pci/controller/dwc/pcie-qcom.c | 116 +++++++++++++++++++++- 2 files changed, 126 insertions(+), 4 deletions(-)
If the endpoint device state is D0 and irq's are not freed, then kernel try to mask interrupts in system suspend path by writing in to the vector table (for MSIX interrupts) and config space (for MSI's). These transactions are initiated in the pm suspend after pcie clocks got disabled as part of platform driver pm suspend call. Due to it, these transactions are resulting in un-clocked access and eventually to crashes. So added a logic in qcom driver to restrict these unclocked access. And updated the logic to check the link state before masking or unmasking the interrupts. Krishna chaitanya chundru (2): PCI: qcom: Add system PM support PCI: qcom: Restrict pci transactions after pci suspend drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++- drivers/pci/controller/dwc/pcie-qcom.c | 114 +++++++++++++++++++++- 2 files changed, 124 insertions(+), 4 deletions(-)
If the endpoint device state is D0 and irq's are not freed, then kernel try to mask interrupts in system suspend path by writing in to the vector table (for MSIX interrupts) and config space (for MSI's). These transactions are initiated in the pm suspend after pcie clocks got disabled as part of platform driver pm suspend call. Due to it, these transactions are resulting in un-clocked access and eventually to crashes. So added a logic in qcom driver to restrict these unclocked access. And updated the logic to check the link state before masking or unmasking the interrupts. Krishna chaitanya chundru (2): PCI: qcom: Add system PM support PCI: qcom: Restrict pci transactions after pci suspend drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++- drivers/pci/controller/dwc/pcie-qcom.c | 121 +++++++++++++++++++++- 2 files changed, 131 insertions(+), 4 deletions(-)
On 06/07/2022 17:40, Krishna chaitanya chundru wrote: > If the endpoint device state is D0 and irq's are not freed, then > kernel try to mask interrupts in system suspend path by writing > in to the vector table (for MSIX interrupts) and config space (for MSI's). > > These transactions are initiated in the pm suspend after pcie clocks got > disabled as part of platform driver pm suspend call. Due to it, these > transactions are resulting in un-clocked access and eventually to crashes. > > So added a logic in qcom driver to restrict these unclocked access. > And updated the logic to check the link state before masking > or unmasking the interrupts. Please do not send new versions as replies to previous ones. This breaks threading for the reviewers. > Krishna chaitanya chundru (2): > PCI: qcom: Add system PM support > PCI: qcom: Restrict pci transactions after pci suspend > > drivers/pci/controller/dwc/pcie-designware-host.c | 14 ++- > drivers/pci/controller/dwc/pcie-qcom.c | 121 +++++++++++++++++++++- > 2 files changed, 131 insertions(+), 4 deletions(-)