Message ID | 20220704112739.3020516-1-pierre.gondois@arm.com (mailing list archive) |
---|---|
Headers | show |
Series | qcom-cpufreq-hw LMH irq/hotplug interractions | expand |
On 04-07-22, 13:27, Pierre Gondois wrote: > v2: > - Rebased on v5.19-rc5 > - Changed irq checks from '< 0' to '<= 0' to be aligned > > The patch-set was tested on a rb5 with an old firmware version: > UEFI Ver : 5.0.210817.BOOT.XF.3.2-00354-SM8250-1 > Build Info : 64b Aug 17 2021 23:35:39 > > commit ffd6cc92ab9c ("arm64: dts: qcom: sm8250: add description of dcvsh > interrupts") > enables DCVS (Dynamic Clock and Voltage Scaling) for sm8250 chips > (so rb5 included). As no LMH (Limits Management Hardware) interrupts > were seen, the firmware used for testing should not be able support > them. > > This patch-set should still contain relevant modifications regarding > LMH interrupts and CPU hotplug. Still, it would be good to test > it on a platform which actually uses LMH interrupts. > > Pierre Gondois (4): > cpufreq: qcom-hw: Reset cancel_throttle when policy is re-enabled > cpufreq: qcom-hw: Disable LMH irq when disabling policy > cpufreq: qcom-hw: Remove deprecated irq_set_affinity_hint() call > cpufreq: Change order of online() CB and policy->cpus modification > > drivers/cpufreq/cpufreq.c | 6 +++--- > drivers/cpufreq/qcom-cpufreq-hw.c | 11 ++++++++--- > 2 files changed, 11 insertions(+), 6 deletions(-) Applied. Thanks.