| Message ID | 20220710115248.190280-7-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | Add support for RZ/N1 SJA1000 CAN controller | expand |
On 10.07.2022 12:52:48, Biju Das wrote: > The SJA1000 CAN controller on RZ/N1 SoC has no clock divider register > (CDR) support compared to others. > > This patch adds support for RZ/N1 SJA1000 CAN Controller, by adding > SoC specific compatible to handle this difference as well as using > clk framework to retrieve the CAN clock frequency. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > v3->v4: > * Updated commit description. > * Updated clock handling as per bindings. > v2->v3: > * No change. > v1->v2: > * Updated commit description as SJA1000_NO_HW_LOOPBACK_QUIRK is removed > * Added error handling on clk error path > * Started using "devm_clk_get_optional_enabled" for clk get,prepare and enable. Due to the use of the devm_clk_get_optional_enabled(), this patch has to wait until devm_clk_get_optional_enabled() hits net-next/master, which will be probably for the v5.21 merge window. We either have to wait or you have to manually enable and disable the clock. regards, Marc
Hi Marc, Thanks for the feedback. > Subject: Re: [PATCH v4 6/6] can: sja1000: Add support for RZ/N1 SJA1000 > CAN Controller > > On 10.07.2022 12:52:48, Biju Das wrote: > > The SJA1000 CAN controller on RZ/N1 SoC has no clock divider register > > (CDR) support compared to others. > > > > This patch adds support for RZ/N1 SJA1000 CAN Controller, by adding > > SoC specific compatible to handle this difference as well as using clk > > framework to retrieve the CAN clock frequency. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > v3->v4: > > * Updated commit description. > > * Updated clock handling as per bindings. > > v2->v3: > > * No change. > > v1->v2: > > * Updated commit description as SJA1000_NO_HW_LOOPBACK_QUIRK is > > removed > > * Added error handling on clk error path > > * Started using "devm_clk_get_optional_enabled" for clk get,prepare > and enable. > > Due to the use of the devm_clk_get_optional_enabled(), this patch has to > wait until devm_clk_get_optional_enabled() hits net-next/master, which > will be probably for the v5.21 merge window. OK, will wait for 5.21 merge window, as this driver is the first user for this API. Cheers, Biju
On 12.07.2022 13:03:49, Biju Das wrote: > > Due to the use of the devm_clk_get_optional_enabled(), this patch has to > > wait until devm_clk_get_optional_enabled() hits net-next/master, which > > will be probably for the v5.21 merge window. > > OK, will wait for 5.21 merge window, as this driver is the first user for this > API. I've applied patches 1...5, please repost patch 6 after devm_clk_get_optional_enabled() has been merged to linus/master. regards, Marc
Hi Marc, > Subject: Re: [PATCH v4 6/6] can: sja1000: Add support for RZ/N1 SJA1000 CAN > Controller > > On 12.07.2022 13:03:49, Biju Das wrote: > > > Due to the use of the devm_clk_get_optional_enabled(), this patch > > > has to wait until devm_clk_get_optional_enabled() hits > > > net-next/master, which will be probably for the v5.21 merge window. > > > > OK, will wait for 5.21 merge window, as this driver is the first user > > for this API. > > I've applied patches 1...5, please repost patch 6 after > devm_clk_get_optional_enabled() has been merged to linus/master. Thanks. Will repost patch#6. Cheers, Biju
On 10.07.2022 12:52:48, Biju Das wrote: > The SJA1000 CAN controller on RZ/N1 SoC has no clock divider register > (CDR) support compared to others. > > This patch adds support for RZ/N1 SJA1000 CAN Controller, by adding > SoC specific compatible to handle this difference as well as using > clk framework to retrieve the CAN clock frequency. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Applied to linux-can-next. regards, Marc
diff --git a/drivers/net/can/sja1000/sja1000_platform.c b/drivers/net/can/sja1000/sja1000_platform.c index 81bc741905fd..6779d5357069 100644 --- a/drivers/net/can/sja1000/sja1000_platform.c +++ b/drivers/net/can/sja1000/sja1000_platform.c @@ -14,6 +14,7 @@ #include <linux/irq.h> #include <linux/can/dev.h> #include <linux/can/platform/sja1000.h> +#include <linux/clk.h> #include <linux/io.h> #include <linux/of.h> #include <linux/of_device.h> @@ -103,6 +104,11 @@ static void sp_technologic_init(struct sja1000_priv *priv, struct device_node *o spin_lock_init(&tp->io_lock); } +static void sp_rzn1_init(struct sja1000_priv *priv, struct device_node *of) +{ + priv->flags = SJA1000_QUIRK_NO_CDR_REG; +} + static void sp_populate(struct sja1000_priv *priv, struct sja1000_platform_data *pdata, unsigned long resource_mem_flags) @@ -153,11 +159,13 @@ static void sp_populate_of(struct sja1000_priv *priv, struct device_node *of) priv->write_reg = sp_write_reg8; } - err = of_property_read_u32(of, "nxp,external-clock-frequency", &prop); - if (!err) - priv->can.clock.freq = prop / 2; - else - priv->can.clock.freq = SP_CAN_CLOCK; /* default */ + if (!priv->can.clock.freq) { + err = of_property_read_u32(of, "nxp,external-clock-frequency", &prop); + if (!err) + priv->can.clock.freq = prop / 2; + else + priv->can.clock.freq = SP_CAN_CLOCK; /* default */ + } err = of_property_read_u32(of, "nxp,tx-output-mode", &prop); if (!err) @@ -192,8 +200,13 @@ static struct sja1000_of_data technologic_data = { .init = sp_technologic_init, }; +static struct sja1000_of_data renesas_data = { + .init = sp_rzn1_init, +}; + static const struct of_device_id sp_of_table[] = { { .compatible = "nxp,sja1000", .data = NULL, }, + { .compatible = "renesas,rzn1-sja1000", .data = &renesas_data, }, { .compatible = "technologic,sja1000", .data = &technologic_data, }, { /* sentinel */ }, }; @@ -210,6 +223,7 @@ static int sp_probe(struct platform_device *pdev) struct device_node *of = pdev->dev.of_node; const struct sja1000_of_data *of_data = NULL; size_t priv_sz = 0; + struct clk *clk; pdata = dev_get_platdata(&pdev->dev); if (!pdata && !of) { @@ -234,6 +248,11 @@ static int sp_probe(struct platform_device *pdev) irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; + + clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(clk), + "CAN clk operation failed"); } else { res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (!res_irq) @@ -262,6 +281,15 @@ static int sp_probe(struct platform_device *pdev) priv->reg_base = addr; if (of) { + if (clk) { + priv->can.clock.freq = clk_get_rate(clk) / 2; + if (!priv->can.clock.freq) { + err = -EINVAL; + dev_err(&pdev->dev, "Zero CAN clk rate"); + goto exit_free; + } + } + sp_populate_of(priv, of); if (of_data && of_data->init)
The SJA1000 CAN controller on RZ/N1 SoC has no clock divider register (CDR) support compared to others. This patch adds support for RZ/N1 SJA1000 CAN Controller, by adding SoC specific compatible to handle this difference as well as using clk framework to retrieve the CAN clock frequency. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- v3->v4: * Updated commit description. * Updated clock handling as per bindings. v2->v3: * No change. v1->v2: * Updated commit description as SJA1000_NO_HW_LOOPBACK_QUIRK is removed * Added error handling on clk error path * Started using "devm_clk_get_optional_enabled" for clk get,prepare and enable. --- drivers/net/can/sja1000/sja1000_platform.c | 38 +++++++++++++++++++--- 1 file changed, 33 insertions(+), 5 deletions(-)