| Message ID | 20220630100241.35233-1-samuel@sholland.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add PLIC support for Renesas RZ/Five SoC / Fix T-HEAD PLIC edge flow | expand |
On 2022-06-30 11:02, Samuel Holland wrote: > This patch series adds PLIC support for Renesas RZ/Five SoC. > > Since the T-HEAD C900 PLIC has the same behavior, it also applies the > fix for that variant. > > This series is an update of v2 of the RZ/Five series[0], and replaces > the separate T-HEAD series[1]. > > [0]: > https://lore.kernel.org/linux-riscv/20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ > [1]: > https://lore.kernel.org/linux-riscv/20220627051257.38543-1-samuel@sholland.org/ > > Changes in v3: > - Add a more detailed explanation for why #interrupt-cells differs > - Add andestech,nceplic100 as a fallback compatible > - Separate the conditional part of the binding into two blocks (one > for > the PLIC implementation and the other for the SoC integration) > - Use a quirk bit for selecting the flow instead of a variant ID > - Use the andestech,nceplic100 compatible to select the new behavior > - Use handle_edge_irq instead of handle_fasteoi_ack_irq so .irq_ack > always gets called > - Do not set the handler name, as RISC-V selects > GENERIC_IRQ_SHOW_LEVEL > - Use the same name for plic_edge_chip as plic_chip > > Changes in v2: > - Fixed review comments pointed by Marc and Krzysztof. > > Changes in v1: > - Fixed review comments pointed by Rob and Geert. > - Changed implementation for EDGE interrupt handling on Renesas > RZ/Five > SoC. > > Lad Prabhakar (2): > dt-bindings: interrupt-controller: sifive,plic: Document Renesas > RZ/Five SoC > irqchip/sifive-plic: Add support for Renesas RZ/Five SoC > > Samuel Holland (2): > dt-bindings: interrupt-controller: Require trigger type for T-HEAD > PLIC > irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling > > .../sifive,plic-1.0.0.yaml | 65 +++++++++++++-- > drivers/irqchip/irq-sifive-plic.c | 80 +++++++++++++++++-- > 2 files changed, 135 insertions(+), 10 deletions(-) I'm going to provisionally queue this into -next so that it can get some testing. I'd still want the DT changes to be Ack'ed before the next merge window though. Thanks, M.
On Fri, 01 Jul 2022 07:28:48 PDT (-0700), Marc Zyngier wrote: > On 2022-06-30 11:02, Samuel Holland wrote: >> This patch series adds PLIC support for Renesas RZ/Five SoC. >> >> Since the T-HEAD C900 PLIC has the same behavior, it also applies the >> fix for that variant. >> >> This series is an update of v2 of the RZ/Five series[0], and replaces >> the separate T-HEAD series[1]. >> >> [0]: >> https://lore.kernel.org/linux-riscv/20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ >> [1]: >> https://lore.kernel.org/linux-riscv/20220627051257.38543-1-samuel@sholland.org/ >> >> Changes in v3: >> - Add a more detailed explanation for why #interrupt-cells differs >> - Add andestech,nceplic100 as a fallback compatible >> - Separate the conditional part of the binding into two blocks (one >> for >> the PLIC implementation and the other for the SoC integration) >> - Use a quirk bit for selecting the flow instead of a variant ID >> - Use the andestech,nceplic100 compatible to select the new behavior >> - Use handle_edge_irq instead of handle_fasteoi_ack_irq so .irq_ack >> always gets called >> - Do not set the handler name, as RISC-V selects >> GENERIC_IRQ_SHOW_LEVEL >> - Use the same name for plic_edge_chip as plic_chip >> >> Changes in v2: >> - Fixed review comments pointed by Marc and Krzysztof. >> >> Changes in v1: >> - Fixed review comments pointed by Rob and Geert. >> - Changed implementation for EDGE interrupt handling on Renesas >> RZ/Five >> SoC. >> >> Lad Prabhakar (2): >> dt-bindings: interrupt-controller: sifive,plic: Document Renesas >> RZ/Five SoC >> irqchip/sifive-plic: Add support for Renesas RZ/Five SoC >> >> Samuel Holland (2): >> dt-bindings: interrupt-controller: Require trigger type for T-HEAD >> PLIC >> irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling >> >> .../sifive,plic-1.0.0.yaml | 65 +++++++++++++-- >> drivers/irqchip/irq-sifive-plic.c | 80 +++++++++++++++++-- >> 2 files changed, 135 insertions(+), 10 deletions(-) > > I'm going to provisionally queue this into -next so that it > can get some testing. I'd still want the DT changes to be > Ack'ed before the next merge window though. +David, as IIRC he still tests on SiFive hardware. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Though I also wait for Rob on DT stuff (I saw the other thread), so not sure that helps any. Thanks!
On 13/07/2022 04:19, Palmer Dabbelt wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > On Fri, 01 Jul 2022 07:28:48 PDT (-0700), Marc Zyngier wrote: >> On 2022-06-30 11:02, Samuel Holland wrote: >>> This patch series adds PLIC support for Renesas RZ/Five SoC. >>> >>> Since the T-HEAD C900 PLIC has the same behavior, it also applies the >>> fix for that variant. >>> >>> This series is an update of v2 of the RZ/Five series[0], and replaces >>> the separate T-HEAD series[1]. >>> >>> [0]: >>> https://lore.kernel.org/linux-riscv/20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ >>> [1]: >>> https://lore.kernel.org/linux-riscv/20220627051257.38543-1-samuel@sholland.org/ >>> >>> Changes in v3: >>> - Add a more detailed explanation for why #interrupt-cells differs >>> - Add andestech,nceplic100 as a fallback compatible >>> - Separate the conditional part of the binding into two blocks (one >>> for >>> the PLIC implementation and the other for the SoC integration) >>> - Use a quirk bit for selecting the flow instead of a variant ID >>> - Use the andestech,nceplic100 compatible to select the new behavior >>> - Use handle_edge_irq instead of handle_fasteoi_ack_irq so .irq_ack >>> always gets called >>> - Do not set the handler name, as RISC-V selects >>> GENERIC_IRQ_SHOW_LEVEL >>> - Use the same name for plic_edge_chip as plic_chip >>> >>> Changes in v2: >>> - Fixed review comments pointed by Marc and Krzysztof. >>> >>> Changes in v1: >>> - Fixed review comments pointed by Rob and Geert. >>> - Changed implementation for EDGE interrupt handling on Renesas >>> RZ/Five >>> SoC. >>> >>> Lad Prabhakar (2): >>> dt-bindings: interrupt-controller: sifive,plic: Document Renesas >>> RZ/Five SoC >>> irqchip/sifive-plic: Add support for Renesas RZ/Five SoC >>> >>> Samuel Holland (2): >>> dt-bindings: interrupt-controller: Require trigger type for T-HEAD >>> PLIC >>> irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling >>> >>> .../sifive,plic-1.0.0.yaml | 65 +++++++++++++-- >>> drivers/irqchip/irq-sifive-plic.c | 80 +++++++++++++++++-- >>> 2 files changed, 135 insertions(+), 10 deletions(-) >> >> I'm going to provisionally queue this into -next so that it >> can get some testing. I'd still want the DT changes to be >> Ack'ed before the next merge window though. > > +David, as IIRC he still tests on SiFive hardware. Not David, but FWIW: I have not done any specific testing, but I've been running various -next revisions since this was put in there (on PolarFire & u540) and have not noticed anything obviously wrong. Thanks, Conor. > > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> > > Though I also wait for Rob on DT stuff (I saw the other thread), so not > sure that helps any. > > Thanks! > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
This patch series adds PLIC support for Renesas RZ/Five SoC. Since the T-HEAD C900 PLIC has the same behavior, it also applies the fix for that variant. This series is an update of v2 of the RZ/Five series[0], and replaces the separate T-HEAD series[1]. [0]: https://lore.kernel.org/linux-riscv/20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ [1]: https://lore.kernel.org/linux-riscv/20220627051257.38543-1-samuel@sholland.org/ Changes in v3: - Add a more detailed explanation for why #interrupt-cells differs - Add andestech,nceplic100 as a fallback compatible - Separate the conditional part of the binding into two blocks (one for the PLIC implementation and the other for the SoC integration) - Use a quirk bit for selecting the flow instead of a variant ID - Use the andestech,nceplic100 compatible to select the new behavior - Use handle_edge_irq instead of handle_fasteoi_ack_irq so .irq_ack always gets called - Do not set the handler name, as RISC-V selects GENERIC_IRQ_SHOW_LEVEL - Use the same name for plic_edge_chip as plic_chip Changes in v2: - Fixed review comments pointed by Marc and Krzysztof. Changes in v1: - Fixed review comments pointed by Rob and Geert. - Changed implementation for EDGE interrupt handling on Renesas RZ/Five SoC. Lad Prabhakar (2): dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC irqchip/sifive-plic: Add support for Renesas RZ/Five SoC Samuel Holland (2): dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling .../sifive,plic-1.0.0.yaml | 65 +++++++++++++-- drivers/irqchip/irq-sifive-plic.c | 80 +++++++++++++++++-- 2 files changed, 135 insertions(+), 10 deletions(-)