| Message ID | 20220715175155.3567243-2-mail@conchuod.ie (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Fix RISC-V's arch-topology reporting | expand |
On Fri, Jul 15, 2022 at 06:51:55PM +0100, Conor Dooley wrote: > From: Conor Dooley <conor.dooley@microchip.com> > > arm64's method of defining a default cpu topology requires only minimal > changes to apply to RISC-V also. The current arm64 implementation exits > early in a uniprocessor configuration by reading MPIDR & claiming that > uniprocessor can rely on the default values. > > This is appears to be a hangover from prior to '3102bc0e6ac7 ("arm64: > topology: Stop using MPIDR for topology information")', because the > current code just assigns default values for multiprocessor systems. > > With the MPIDR references removed, store_cpu_topolgy() can be moved to > the common arch_topology code. > > CC: stable@vger.kernel.org I'd quantify how far back you want this to go. IIUC based on the Fixes tag in the other patch, it should stop at 5.4. If you send a pull request instead and have a fixed commit id, you could add it as a prerequisite on the following patch without a cc stable here. Either way: Acked-by: Catalin Marinas <catalin.marinas@arm.com>
On 19/07/2022 12:41, Catalin Marinas wrote: > On Fri, Jul 15, 2022 at 06:51:55PM +0100, Conor Dooley wrote: >> From: Conor Dooley <conor.dooley@microchip.com> >> >> arm64's method of defining a default cpu topology requires only minimal >> changes to apply to RISC-V also. The current arm64 implementation exits >> early in a uniprocessor configuration by reading MPIDR & claiming that >> uniprocessor can rely on the default values. >> >> This is appears to be a hangover from prior to '3102bc0e6ac7 ("arm64: >> topology: Stop using MPIDR for topology information")', because the >> current code just assigns default values for multiprocessor systems. >> >> With the MPIDR references removed, store_cpu_topolgy() can be moved to >> the common arch_topology code. >> >> CC: stable@vger.kernel.org > > I'd quantify how far back you want this to go. IIUC based on the Fixes > tag in the other patch, it should stop at 5.4. If you send a pull > request instead and have a fixed commit id, you could add it as a > prerequisite on the following patch without a cc stable here. I guess a PR might be the easiest way for it anyway, so that both yourself and Palmer could merge it? > > Either way: > > Acked-by: Catalin Marinas <catalin.marinas@arm.com> Thanks.
On Tue, Jul 19, 2022 at 11:51:04AM +0000, Conor.Dooley@microchip.com wrote: > On 19/07/2022 12:41, Catalin Marinas wrote: > > On Fri, Jul 15, 2022 at 06:51:55PM +0100, Conor Dooley wrote: > >> From: Conor Dooley <conor.dooley@microchip.com> > >> > >> arm64's method of defining a default cpu topology requires only minimal > >> changes to apply to RISC-V also. The current arm64 implementation exits > >> early in a uniprocessor configuration by reading MPIDR & claiming that > >> uniprocessor can rely on the default values. > >> > >> This is appears to be a hangover from prior to '3102bc0e6ac7 ("arm64: > >> topology: Stop using MPIDR for topology information")', because the > >> current code just assigns default values for multiprocessor systems. > >> > >> With the MPIDR references removed, store_cpu_topolgy() can be moved to > >> the common arch_topology code. > >> > >> CC: stable@vger.kernel.org > > > > I'd quantify how far back you want this to go. IIUC based on the Fixes > > tag in the other patch, it should stop at 5.4. If you send a pull > > request instead and have a fixed commit id, you could add it as a > > prerequisite on the following patch without a cc stable here. > > I guess a PR might be the easiest way for it anyway, so that both > yourself and Palmer could merge it? I guess so, a stable branch would do. Note that Will is handling the upcoming merging window.
On Fri, Jul 15, 2022 at 10:53 AM Conor Dooley <mail@conchuod.ie> wrote: > > From: Conor Dooley <conor.dooley@microchip.com> > > arm64's method of defining a default cpu topology requires only minimal > changes to apply to RISC-V also. The current arm64 implementation exits > early in a uniprocessor configuration by reading MPIDR & claiming that > uniprocessor can rely on the default values. > > This is appears to be a hangover from prior to '3102bc0e6ac7 ("arm64: > topology: Stop using MPIDR for topology information")', because the > current code just assigns default values for multiprocessor systems. > > With the MPIDR references removed, store_cpu_topolgy() can be moved to > the common arch_topology code. > > CC: stable@vger.kernel.org > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> > --- > arch/arm64/kernel/topology.c | 40 ------------------------------------ > drivers/base/arch_topology.c | 19 +++++++++++++++++ > 2 files changed, 19 insertions(+), 40 deletions(-) > > diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c > index 869ffc4d4484..7889a00f5487 100644 > --- a/arch/arm64/kernel/topology.c > +++ b/arch/arm64/kernel/topology.c > @@ -22,46 +22,6 @@ > #include <asm/cputype.h> > #include <asm/topology.h> > > -void store_cpu_topology(unsigned int cpuid) > -{ > - struct cpu_topology *cpuid_topo = &cpu_topology[cpuid]; > - u64 mpidr; > - > - if (cpuid_topo->package_id != -1) > - goto topology_populated; > - > - mpidr = read_cpuid_mpidr(); > - > - /* Uniprocessor systems can rely on default topology values */ > - if (mpidr & MPIDR_UP_BITMASK) > - return; > - > - /* > - * This would be the place to create cpu topology based on MPIDR. > - * > - * However, it cannot be trusted to depict the actual topology; some > - * pieces of the architecture enforce an artificial cap on Aff0 values > - * (e.g. GICv3's ICC_SGI1R_EL1 limits it to 15), leading to an > - * artificial cycling of Aff1, Aff2 and Aff3 values. IOW, these end up > - * having absolutely no relationship to the actual underlying system > - * topology, and cannot be reasonably used as core / package ID. > - * > - * If the MT bit is set, Aff0 *could* be used to define a thread ID, but > - * we still wouldn't be able to obtain a sane core ID. This means we > - * need to entirely ignore MPIDR for any topology deduction. > - */ > - cpuid_topo->thread_id = -1; > - cpuid_topo->core_id = cpuid; > - cpuid_topo->package_id = cpu_to_node(cpuid); > - > - pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n", > - cpuid, cpuid_topo->package_id, cpuid_topo->core_id, > - cpuid_topo->thread_id, mpidr); > - > -topology_populated: > - update_siblings_masks(cpuid); > -} > - > #ifdef CONFIG_ACPI > static bool __init acpi_cpu_is_threaded(int cpu) > { > diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c > index 0424b59b695e..0e2c6b30dd69 100644 > --- a/drivers/base/arch_topology.c > +++ b/drivers/base/arch_topology.c > @@ -841,4 +841,23 @@ void __init init_cpu_topology(void) > return; > } > } > + > +void store_cpu_topology(unsigned int cpuid) > +{ > + struct cpu_topology *cpuid_topo = &cpu_topology[cpuid]; > + > + if (cpuid_topo->package_id != -1) > + goto topology_populated; > + > + cpuid_topo->thread_id = -1; > + cpuid_topo->core_id = cpuid; > + cpuid_topo->package_id = cpu_to_node(cpuid); > + > + pr_debug("CPU%u: package %d core %d thread %d\n", > + cpuid, cpuid_topo->package_id, cpuid_topo->core_id, > + cpuid_topo->thread_id); > + > +topology_populated: > + update_siblings_masks(cpuid); > +} > #endif > -- > 2.37.1 > LGTM. Reviewed-by: Atish Patra <atishp@rivosinc.com> -- Regards, Atish
diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 869ffc4d4484..7889a00f5487 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -22,46 +22,6 @@ #include <asm/cputype.h> #include <asm/topology.h> -void store_cpu_topology(unsigned int cpuid) -{ - struct cpu_topology *cpuid_topo = &cpu_topology[cpuid]; - u64 mpidr; - - if (cpuid_topo->package_id != -1) - goto topology_populated; - - mpidr = read_cpuid_mpidr(); - - /* Uniprocessor systems can rely on default topology values */ - if (mpidr & MPIDR_UP_BITMASK) - return; - - /* - * This would be the place to create cpu topology based on MPIDR. - * - * However, it cannot be trusted to depict the actual topology; some - * pieces of the architecture enforce an artificial cap on Aff0 values - * (e.g. GICv3's ICC_SGI1R_EL1 limits it to 15), leading to an - * artificial cycling of Aff1, Aff2 and Aff3 values. IOW, these end up - * having absolutely no relationship to the actual underlying system - * topology, and cannot be reasonably used as core / package ID. - * - * If the MT bit is set, Aff0 *could* be used to define a thread ID, but - * we still wouldn't be able to obtain a sane core ID. This means we - * need to entirely ignore MPIDR for any topology deduction. - */ - cpuid_topo->thread_id = -1; - cpuid_topo->core_id = cpuid; - cpuid_topo->package_id = cpu_to_node(cpuid); - - pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n", - cpuid, cpuid_topo->package_id, cpuid_topo->core_id, - cpuid_topo->thread_id, mpidr); - -topology_populated: - update_siblings_masks(cpuid); -} - #ifdef CONFIG_ACPI static bool __init acpi_cpu_is_threaded(int cpu) { diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c index 0424b59b695e..0e2c6b30dd69 100644 --- a/drivers/base/arch_topology.c +++ b/drivers/base/arch_topology.c @@ -841,4 +841,23 @@ void __init init_cpu_topology(void) return; } } + +void store_cpu_topology(unsigned int cpuid) +{ + struct cpu_topology *cpuid_topo = &cpu_topology[cpuid]; + + if (cpuid_topo->package_id != -1) + goto topology_populated; + + cpuid_topo->thread_id = -1; + cpuid_topo->core_id = cpuid; + cpuid_topo->package_id = cpu_to_node(cpuid); + + pr_debug("CPU%u: package %d core %d thread %d\n", + cpuid, cpuid_topo->package_id, cpuid_topo->core_id, + cpuid_topo->thread_id); + +topology_populated: + update_siblings_masks(cpuid); +} #endif