diff mbox series

[v5,01/17] perf: Add SNOOP_PEER flag to perf mem data struct

Message ID 20220604042820.2270916-2-leo.yan@linaro.org (mailing list archive)
State New, archived
Headers show
Series perf c2c: Support data source and display for Arm64 | expand

Commit Message

Leo Yan June 4, 2022, 4:28 a.m. UTC 
From: Ali Saidi <alisaidi@amazon.com>

Add a flag to the perf mem data struct to signal that a request caused a
cache-to-cache transfer of a line from a peer of the requestor and
wasn't sourced from a lower cache level.  The line being moved from one
peer cache to another has latency and performance implications. On Arm64
Neoverse systems the data source can indicate a cache-to-cache transfer
but not if the line is dirty or clean, so instead of overloading HITM
define a new flag that indicates this type of transfer.

Signed-off-by: Ali Saidi <alisaidi@amazon.com>
Reviewed-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Kajol Jain<kjain@linux.ibm.com>
---
 include/uapi/linux/perf_event.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Arnaldo Carvalho de Melo July 20, 2022, 6:45 p.m. UTC | #1 
Em Sat, Jun 04, 2022 at 12:28:04PM +0800, Leo Yan escreveu:
> From: Ali Saidi <alisaidi@amazon.com>
> 
> Add a flag to the perf mem data struct to signal that a request caused a
> cache-to-cache transfer of a line from a peer of the requestor and
> wasn't sourced from a lower cache level.  The line being moved from one
> peer cache to another has latency and performance implications. On Arm64
> Neoverse systems the data source can indicate a cache-to-cache transfer
> but not if the line is dirty or clean, so instead of overloading HITM
> define a new flag that indicates this type of transfer.
> 
> Signed-off-by: Ali Saidi <alisaidi@amazon.com>
> Reviewed-by: Leo Yan <leo.yan@linaro.org>
> Reviewed-by: Kajol Jain<kjain@linux.ibm.com>

Hey, any knews about this going upstream? PeterZ?

- Arnaldo

> ---
>  include/uapi/linux/perf_event.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
> index d37629dbad72..7b88bfd097dc 100644
> --- a/include/uapi/linux/perf_event.h
> +++ b/include/uapi/linux/perf_event.h
> @@ -1310,7 +1310,7 @@ union perf_mem_data_src {
>  #define PERF_MEM_SNOOP_SHIFT	19
>  
>  #define PERF_MEM_SNOOPX_FWD	0x01 /* forward */
> -/* 1 free */
> +#define PERF_MEM_SNOOPX_PEER	0x02 /* xfer from peer */
>  #define PERF_MEM_SNOOPX_SHIFT  38
>  
>  /* locked instruction */
> -- 
> 2.25.1
Arnaldo Carvalho de Melo July 20, 2022, 6:46 p.m. UTC | #2 
Em Wed, Jul 20, 2022 at 03:45:51PM -0300, Arnaldo Carvalho de Melo escreveu:
> Em Sat, Jun 04, 2022 at 12:28:04PM +0800, Leo Yan escreveu:
> > From: Ali Saidi <alisaidi@amazon.com>
> > 
> > Add a flag to the perf mem data struct to signal that a request caused a
> > cache-to-cache transfer of a line from a peer of the requestor and
> > wasn't sourced from a lower cache level.  The line being moved from one
> > peer cache to another has latency and performance implications. On Arm64
> > Neoverse systems the data source can indicate a cache-to-cache transfer
> > but not if the line is dirty or clean, so instead of overloading HITM
> > define a new flag that indicates this type of transfer.
> > 
> > Signed-off-by: Ali Saidi <alisaidi@amazon.com>
> > Reviewed-by: Leo Yan <leo.yan@linaro.org>
> > Reviewed-by: Kajol Jain<kjain@linux.ibm.com>
> 
> Hey, any knews about this going upstream? PeterZ?

Just took a look and it isn't in tip/master.

- Arnaldo
 
> > ---
> >  include/uapi/linux/perf_event.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
> > index d37629dbad72..7b88bfd097dc 100644
> > --- a/include/uapi/linux/perf_event.h
> > +++ b/include/uapi/linux/perf_event.h
> > @@ -1310,7 +1310,7 @@ union perf_mem_data_src {
> >  #define PERF_MEM_SNOOP_SHIFT	19
> >  
> >  #define PERF_MEM_SNOOPX_FWD	0x01 /* forward */
> > -/* 1 free */
> > +#define PERF_MEM_SNOOPX_PEER	0x02 /* xfer from peer */
> >  #define PERF_MEM_SNOOPX_SHIFT  38
> >  
> >  /* locked instruction */
> > -- 
> > 2.25.1
> 
> -- 
> 
> - Arnaldo
Leo Yan July 21, 2022, 12:27 a.m. UTC | #3 
On Wed, Jul 20, 2022 at 03:46:49PM -0300, Arnaldo Carvalho de Melo wrote:
> Em Wed, Jul 20, 2022 at 03:45:51PM -0300, Arnaldo Carvalho de Melo escreveu:
> > Em Sat, Jun 04, 2022 at 12:28:04PM +0800, Leo Yan escreveu:
> > > From: Ali Saidi <alisaidi@amazon.com>
> > > 
> > > Add a flag to the perf mem data struct to signal that a request caused a
> > > cache-to-cache transfer of a line from a peer of the requestor and
> > > wasn't sourced from a lower cache level.  The line being moved from one
> > > peer cache to another has latency and performance implications. On Arm64
> > > Neoverse systems the data source can indicate a cache-to-cache transfer
> > > but not if the line is dirty or clean, so instead of overloading HITM
> > > define a new flag that indicates this type of transfer.
> > > 
> > > Signed-off-by: Ali Saidi <alisaidi@amazon.com>
> > > Reviewed-by: Leo Yan <leo.yan@linaro.org>
> > > Reviewed-by: Kajol Jain<kjain@linux.ibm.com>
> > 
> > Hey, any knews about this going upstream? PeterZ?
> 
> Just took a look and it isn't in tip/master.

Yeah, this patch is not picked by maintainers.

I confirmed that this patch can be applied cleanly on tip/master
branch.  Peter.Z, could you pick this patch?

Thanks,
Leo
Arnaldo Carvalho de Melo Aug. 8, 2022, 4:40 p.m. UTC | #4 
Em Thu, Jul 21, 2022 at 08:27:19AM +0800, Leo Yan escreveu:
> On Wed, Jul 20, 2022 at 03:46:49PM -0300, Arnaldo Carvalho de Melo wrote:
> > Em Wed, Jul 20, 2022 at 03:45:51PM -0300, Arnaldo Carvalho de Melo escreveu:
> > > Em Sat, Jun 04, 2022 at 12:28:04PM +0800, Leo Yan escreveu:
> > > > From: Ali Saidi <alisaidi@amazon.com>
> > > > 
> > > > Add a flag to the perf mem data struct to signal that a request caused a
> > > > cache-to-cache transfer of a line from a peer of the requestor and
> > > > wasn't sourced from a lower cache level.  The line being moved from one
> > > > peer cache to another has latency and performance implications. On Arm64
> > > > Neoverse systems the data source can indicate a cache-to-cache transfer
> > > > but not if the line is dirty or clean, so instead of overloading HITM
> > > > define a new flag that indicates this type of transfer.
> > > > 
> > > > Signed-off-by: Ali Saidi <alisaidi@amazon.com>
> > > > Reviewed-by: Leo Yan <leo.yan@linaro.org>
> > > > Reviewed-by: Kajol Jain<kjain@linux.ibm.com>
> > > 
> > > Hey, any knews about this going upstream? PeterZ?
> > 
> > Just took a look and it isn't in tip/master.
> 
> Yeah, this patch is not picked by maintainers.
> 
> I confirmed that this patch can be applied cleanly on tip/master
> branch.  Peter.Z, could you pick this patch?

ping.

- Arnaldo
diff mbox series

Patch

diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index d37629dbad72..7b88bfd097dc 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -1310,7 +1310,7 @@  union perf_mem_data_src {
 #define PERF_MEM_SNOOP_SHIFT	19
 
 #define PERF_MEM_SNOOPX_FWD	0x01 /* forward */
-/* 1 free */
+#define PERF_MEM_SNOOPX_PEER	0x02 /* xfer from peer */
 #define PERF_MEM_SNOOPX_SHIFT  38
 
 /* locked instruction */