Message ID | 20220722090609.52364-5-angelogioacchino.delregno@collabora.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | MediaTek Helio X10 MT6795 - Clock drivers | expand |
On 22/07/2022 11:06, AngeloGioacchino Del Regno wrote: > Add the bindings for the clock drivers of the MediaTek Helio X10 > MT6795 SoC. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > .../bindings/clock/mediatek,mt6795-clock.yaml | 66 +++++++++++++++++++ > .../clock/mediatek,mt6795-sys-clock.yaml | 54 +++++++++++++++ > 2 files changed, 120 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml You already got a review tag, didn't you? In v5? Best regards, Krzysztof
Il 23/07/22 22:45, Krzysztof Kozlowski ha scritto: > On 22/07/2022 11:06, AngeloGioacchino Del Regno wrote: >> Add the bindings for the clock drivers of the MediaTek Helio X10 >> MT6795 SoC. >> >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> >> --- >> .../bindings/clock/mediatek,mt6795-clock.yaml | 66 +++++++++++++++++++ >> .../clock/mediatek,mt6795-sys-clock.yaml | 54 +++++++++++++++ >> 2 files changed, 120 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml >> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml > > You already got a review tag, didn't you? In v5? > > I'm sorry, yes I got Rob's review tag in v5 and I somehow forgot to add it to v6 :-( Should I send a v7 for adding back the tag? Angelo
On 25/07/2022 10:13, AngeloGioacchino Del Regno wrote: > I'm sorry, yes I got Rob's review tag in v5 and I somehow forgot to add > it to v6 :-( > > Should I send a v7 for adding back the tag? Yes, because otherwise it will pop-up at Rob's patchwork for a review. Best regards, Krzysztof
On Fri, 22 Jul 2022 11:06:05 +0200, AngeloGioacchino Del Regno wrote: > Add the bindings for the clock drivers of the MediaTek Helio X10 > MT6795 SoC. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > .../bindings/clock/mediatek,mt6795-clock.yaml | 66 +++++++++++++++++++ > .../clock/mediatek,mt6795-sys-clock.yaml | 54 +++++++++++++++ > 2 files changed, 120 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml new file mode 100644 index 000000000000..04469eabc8fa --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt6795-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Functional Clock Controller for MT6795 + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + - Chun-Jie Chen <chun-jie.chen@mediatek.com> + +description: | + The clock architecture in MediaTek like below + PLLs --> + dividers --> + muxes + --> + clock gate + + The devices provide clock gate control in different IP blocks. + +properties: + compatible: + enum: + - mediatek,mt6795-mfgcfg + - mediatek,mt6795-vdecsys + - mediatek,mt6795-vencsys + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + mfgcfg: clock-controller@13000000 { + compatible = "mediatek,mt6795-mfgcfg"; + reg = <0 0x13000000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: clock-controller@16000000 { + compatible = "mediatek,mt6795-vdecsys"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@18000000 { + compatible = "mediatek,mt6795-vencsys"; + reg = <0 0x18000000 0 0x1000>; + #clock-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml new file mode 100644 index 000000000000..378b761237d3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt6795-sys-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek System Clock Controller for MT6795 + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + - Chun-Jie Chen <chun-jie.chen@mediatek.com> + +description: + The Mediatek system clock controller provides various clocks and system + configuration like reset and bus protection on MT6795. + +properties: + compatible: + items: + - enum: + - mediatek,mt6795-apmixedsys + - mediatek,mt6795-infracfg + - mediatek,mt6795-pericfg + - mediatek,mt6795-topckgen + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + topckgen: clock-controller@10000000 { + compatible = "mediatek,mt6795-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + };
Add the bindings for the clock drivers of the MediaTek Helio X10 MT6795 SoC. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- .../bindings/clock/mediatek,mt6795-clock.yaml | 66 +++++++++++++++++++ .../clock/mediatek,mt6795-sys-clock.yaml | 54 +++++++++++++++ 2 files changed, 120 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6795-clock.yaml create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6795-sys-clock.yaml