| Message ID | 20220610174459.615995-1-nick.forrington@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | perf vendor events arm64: Arm Cortex-A78C and X1C | expand |
On 10/06/2022 18:44, Nick Forrington wrote: > Add PMU events for the Arm Cortex-A78C and Arm Cortex-X1C CPUs. > > Events for Arm Cortex-A78C match those for Arm Cortex-A78. > Events for Arm Cortex-X1C match those for Arm Cortex- X1. > > As such, this is just a mapfile change. > > Main ID Register (MIDR) and event data is sourced from the corresponding > Arm Technical Reference Manuals: > > Arm Cortex-A78C > https://developer.arm.com/documentation/102226/ > > Arm Cortex-X1C > https://developer.arm.com/documentation/101968/ > > Signed-off-by: Nick Forrington<nick.forrington@arm.com> Reviewed-by: John Garry <john.garry@huawei.com>
On 13/06/2022 11:09, John Garry wrote: > On 10/06/2022 18:44, Nick Forrington wrote: >> Add PMU events for the Arm Cortex-A78C and Arm Cortex-X1C CPUs. >> >> Events for Arm Cortex-A78C match those for Arm Cortex-A78. >> Events for Arm Cortex-X1C match those for Arm Cortex- X1. >> >> As such, this is just a mapfile change. >> >> Main ID Register (MIDR) and event data is sourced from the corresponding >> Arm Technical Reference Manuals: >> >> Arm Cortex-A78C >> https://developer.arm.com/documentation/102226/ >> >> Arm Cortex-X1C >> https://developer.arm.com/documentation/101968/ >> >> Signed-off-by: Nick Forrington<nick.forrington@arm.com> > > Reviewed-by: John Garry <john.garry@huawei.com> Could this be applied please? Thanks, Nick
Em Thu, Jul 28, 2022 at 05:17:08PM +0100, Nick Forrington escreveu: > On 13/06/2022 11:09, John Garry wrote: > > On 10/06/2022 18:44, Nick Forrington wrote: > > > Add PMU events for the Arm Cortex-A78C and Arm Cortex-X1C CPUs. > > > > > > Events for Arm Cortex-A78C match those for Arm Cortex-A78. > > > Events for Arm Cortex-X1C match those for Arm Cortex- X1. > > > > > > As such, this is just a mapfile change. > > > > > > Main ID Register (MIDR) and event data is sourced from the corresponding > > > Arm Technical Reference Manuals: > > > > > > Arm Cortex-A78C > > > https://developer.arm.com/documentation/102226/ > > > > > > Arm Cortex-X1C > > > https://developer.arm.com/documentation/101968/ > > > > > > Signed-off-by: Nick Forrington<nick.forrington@arm.com> > > > > Reviewed-by: John Garry <john.garry@huawei.com> > > Could this be applied please? Thanks, applied. - Arnaldo
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index ed29e4433c67..406f6edd4e12 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -27,7 +27,9 @@ 0x00000000410fd0d0,v1,arm/cortex-a77,core 0x00000000410fd400,v1,arm/neoverse-v1,core 0x00000000410fd410,v1,arm/cortex-a78,core +0x00000000410fd4b0,v1,arm/cortex-a78,core 0x00000000410fd440,v1,arm/cortex-x1,core +0x00000000410fd4c0,v1,arm/cortex-x1,core 0x00000000410fd460,v1,arm/cortex-a510,core 0x00000000410fd470,v1,arm/cortex-a710,core 0x00000000410fd480,v1,arm/cortex-x2,core
Add PMU events for the Arm Cortex-A78C and Arm Cortex-X1C CPUs. Events for Arm Cortex-A78C match those for Arm Cortex-A78. Events for Arm Cortex-X1C match those for Arm Cortex- X1. As such, this is just a mapfile change. Main ID Register (MIDR) and event data is sourced from the corresponding Arm Technical Reference Manuals: Arm Cortex-A78C https://developer.arm.com/documentation/102226/ Arm Cortex-X1C https://developer.arm.com/documentation/101968/ Signed-off-by: Nick Forrington <nick.forrington@arm.com> --- tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 ++ 1 file changed, 2 insertions(+)