diff mbox series

[13/19] ppc/ppc405: QOM'ify OPBA

Message ID 20220801131039.1693913-14-clg@kaod.org (mailing list archive)
State New, archived
Headers show
Series ppc: QOM'ify 405 board | expand

Commit Message

Cédric Le Goater Aug. 1, 2022, 1:10 p.m. UTC 
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/ppc/ppc405.h    | 12 ++++++++++++
 hw/ppc/ppc405_uc.c | 47 +++++++++++++++++++++++++++-------------------
 2 files changed, 40 insertions(+), 19 deletions(-)

Comments

Daniel Henrique Barboza Aug. 3, 2022, 9:27 a.m. UTC | #1 
On 8/1/22 10:10, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>

>   hw/ppc/ppc405.h    | 12 ++++++++++++
>   hw/ppc/ppc405_uc.c | 47 +++++++++++++++++++++++++++-------------------
>   2 files changed, 40 insertions(+), 19 deletions(-)
> 
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index f1acb37185f5..ebff00bdad80 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -65,6 +65,17 @@ struct ppc4xx_bd_info_t {
>   
>   typedef struct Ppc405SoCState Ppc405SoCState;
>   
> +/* OPB arbitrer */
> +#define TYPE_PPC405_OPBA "ppc405-opba"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
> +struct Ppc405OpbaState {
> +    SysBusDevice parent_obj;
> +
> +    MemoryRegion io;
> +    uint8_t cr;
> +    uint8_t pr;
> +};
> +
>   /* Peripheral controller */
>   #define TYPE_PPC405_EBC "ppc405-ebc"
>   OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
> @@ -219,6 +230,7 @@ struct Ppc405SoCState {
>       Ppc405GpioState gpio;
>       Ppc405DmaState dma;
>       Ppc405EbcState ebc;
> +    Ppc405OpbaState opba;
>   };
>   
>   /* PowerPC 405 core */
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 8d73b8c2dff0..c5de00de7981 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -310,16 +310,10 @@ static void ppc4xx_pob_init(CPUPPCState *env)
>   
>   /*****************************************************************************/
>   /* OPB arbitrer */
> -typedef struct ppc4xx_opba_t ppc4xx_opba_t;
> -struct ppc4xx_opba_t {
> -    MemoryRegion io;
> -    uint8_t cr;
> -    uint8_t pr;
> -};
>   
>   static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
>   {
> -    ppc4xx_opba_t *opba = opaque;
> +    Ppc405OpbaState *opba = PPC405_OPBA(opaque);
>       uint32_t ret;
>   
>       switch (addr) {
> @@ -341,7 +335,7 @@ static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
>   static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,
>                           unsigned size)
>   {
> -    ppc4xx_opba_t *opba = opaque;
> +    Ppc405OpbaState *opba = PPC405_OPBA(opaque);
>   
>       trace_opba_writeb(addr, value);
>   
> @@ -366,25 +360,30 @@ static const MemoryRegionOps opba_ops = {
>       .endianness = DEVICE_BIG_ENDIAN,
>   };
>   
> -static void ppc4xx_opba_reset (void *opaque)
> +static void ppc405_opba_reset(DeviceState *dev)
>   {
> -    ppc4xx_opba_t *opba;
> +    Ppc405OpbaState *opba = PPC405_OPBA(dev);
>   
> -    opba = opaque;
>       opba->cr = 0x00; /* No dynamic priorities - park disabled */
>       opba->pr = 0x11;
>   }
>   
> -static void ppc4xx_opba_init(hwaddr base)
> +static void ppc405_opba_realize(DeviceState *dev, Error **errp)
>   {
> -    ppc4xx_opba_t *opba;
> +    Ppc405OpbaState *s = PPC405_OPBA(dev);
> +    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
>   
> -    trace_opba_init(base);
> +    memory_region_init_io(&s->io, OBJECT(s), &opba_ops, s, "opba", 0x002);
> +    sysbus_init_mmio(sbd, &s->io);
> +}
> +
> +static void ppc405_opba_class_init(ObjectClass *oc, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(oc);
>   
> -    opba = g_new0(ppc4xx_opba_t, 1);
> -    memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
> -    memory_region_add_subregion(get_system_memory(), base, &opba->io);
> -    qemu_register_reset(ppc4xx_opba_reset, opba);
> +    dc->realize = ppc405_opba_realize;
> +    dc->reset = ppc405_opba_reset;
> +    dc->user_creatable = false;
>   }
>   
>   /*****************************************************************************/
> @@ -1434,6 +1433,8 @@ static void ppc405_soc_instance_init(Object *obj)
>       object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
>   
>       object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
> +
> +    object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
>   }
>   
>   static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> @@ -1486,7 +1487,10 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>       ppc4xx_pob_init(env);
>   
>       /* OBP arbitrer */
> -    ppc4xx_opba_init(0xef600600);
> +   if (!sysbus_realize(SYS_BUS_DEVICE(&s->opba), errp)) {
> +        return;
> +    }
> +    sysbus_mmio_map(SYS_BUS_DEVICE(&s->opba), 0, 0xef600600);
>   
>       /* Universal interrupt controller */
>       s->uic = qdev_new(TYPE_PPC_UIC);
> @@ -1598,6 +1602,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
>   
>   static const TypeInfo ppc405_types[] = {
>       {
> +        .name           = TYPE_PPC405_OPBA,
> +        .parent         = TYPE_SYS_BUS_DEVICE,
> +        .instance_size  = sizeof(Ppc405OpbaState),
> +        .class_init     = ppc405_opba_class_init,
> +    }, {
>           .name           = TYPE_PPC405_EBC,
>           .parent         = TYPE_DEVICE,
>           .instance_size  = sizeof(Ppc405EbcState),
diff mbox series

Patch

diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index f1acb37185f5..ebff00bdad80 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -65,6 +65,17 @@  struct ppc4xx_bd_info_t {
 
 typedef struct Ppc405SoCState Ppc405SoCState;
 
+/* OPB arbitrer */
+#define TYPE_PPC405_OPBA "ppc405-opba"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
+struct Ppc405OpbaState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion io;
+    uint8_t cr;
+    uint8_t pr;
+};
+
 /* Peripheral controller */
 #define TYPE_PPC405_EBC "ppc405-ebc"
 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
@@ -219,6 +230,7 @@  struct Ppc405SoCState {
     Ppc405GpioState gpio;
     Ppc405DmaState dma;
     Ppc405EbcState ebc;
+    Ppc405OpbaState opba;
 };
 
 /* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index 8d73b8c2dff0..c5de00de7981 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -310,16 +310,10 @@  static void ppc4xx_pob_init(CPUPPCState *env)
 
 /*****************************************************************************/
 /* OPB arbitrer */
-typedef struct ppc4xx_opba_t ppc4xx_opba_t;
-struct ppc4xx_opba_t {
-    MemoryRegion io;
-    uint8_t cr;
-    uint8_t pr;
-};
 
 static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
 {
-    ppc4xx_opba_t *opba = opaque;
+    Ppc405OpbaState *opba = PPC405_OPBA(opaque);
     uint32_t ret;
 
     switch (addr) {
@@ -341,7 +335,7 @@  static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
 static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,
                         unsigned size)
 {
-    ppc4xx_opba_t *opba = opaque;
+    Ppc405OpbaState *opba = PPC405_OPBA(opaque);
 
     trace_opba_writeb(addr, value);
 
@@ -366,25 +360,30 @@  static const MemoryRegionOps opba_ops = {
     .endianness = DEVICE_BIG_ENDIAN,
 };
 
-static void ppc4xx_opba_reset (void *opaque)
+static void ppc405_opba_reset(DeviceState *dev)
 {
-    ppc4xx_opba_t *opba;
+    Ppc405OpbaState *opba = PPC405_OPBA(dev);
 
-    opba = opaque;
     opba->cr = 0x00; /* No dynamic priorities - park disabled */
     opba->pr = 0x11;
 }
 
-static void ppc4xx_opba_init(hwaddr base)
+static void ppc405_opba_realize(DeviceState *dev, Error **errp)
 {
-    ppc4xx_opba_t *opba;
+    Ppc405OpbaState *s = PPC405_OPBA(dev);
+    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 
-    trace_opba_init(base);
+    memory_region_init_io(&s->io, OBJECT(s), &opba_ops, s, "opba", 0x002);
+    sysbus_init_mmio(sbd, &s->io);
+}
+
+static void ppc405_opba_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
 
-    opba = g_new0(ppc4xx_opba_t, 1);
-    memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
-    memory_region_add_subregion(get_system_memory(), base, &opba->io);
-    qemu_register_reset(ppc4xx_opba_reset, opba);
+    dc->realize = ppc405_opba_realize;
+    dc->reset = ppc405_opba_reset;
+    dc->user_creatable = false;
 }
 
 /*****************************************************************************/
@@ -1434,6 +1433,8 @@  static void ppc405_soc_instance_init(Object *obj)
     object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
 
     object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
+
+    object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
 }
 
 static void ppc405_soc_realize(DeviceState *dev, Error **errp)
@@ -1486,7 +1487,10 @@  static void ppc405_soc_realize(DeviceState *dev, Error **errp)
     ppc4xx_pob_init(env);
 
     /* OBP arbitrer */
-    ppc4xx_opba_init(0xef600600);
+   if (!sysbus_realize(SYS_BUS_DEVICE(&s->opba), errp)) {
+        return;
+    }
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->opba), 0, 0xef600600);
 
     /* Universal interrupt controller */
     s->uic = qdev_new(TYPE_PPC_UIC);
@@ -1598,6 +1602,11 @@  static void ppc405_soc_class_init(ObjectClass *oc, void *data)
 
 static const TypeInfo ppc405_types[] = {
     {
+        .name           = TYPE_PPC405_OPBA,
+        .parent         = TYPE_SYS_BUS_DEVICE,
+        .instance_size  = sizeof(Ppc405OpbaState),
+        .class_init     = ppc405_opba_class_init,
+    }, {
         .name           = TYPE_PPC405_EBC,
         .parent         = TYPE_DEVICE,
         .instance_size  = sizeof(Ppc405EbcState),