| Message ID | 20220803182328.2438598-3-ricarkol@google.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm: pmu: Fixes for bare metal | expand |
Hi Ricardo, On 8/3/22 20:23, Ricardo Koller wrote: > Some registers like the PMOVS reset to an architecturally UNKNOWN value. > Most tests expect them to be reset (mostly zeroed) using pmu_reset(). > Add a pmu_reset() on all the tests that need one. > > As a bonus, fix a couple of comments related to the register state > before a sub-test. > > Signed-off-by: Ricardo Koller <ricarkol@google.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Eric > --- > arm/pmu.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/arm/pmu.c b/arm/pmu.c > index 76156f78..7c5bc259 100644 > --- a/arm/pmu.c > +++ b/arm/pmu.c > @@ -826,7 +826,7 @@ static void test_overflow_interrupt(void) > write_regn_el0(pmevcntr, 1, PRE_OVERFLOW); > isb(); > > - /* interrupts are disabled */ > + /* interrupts are disabled (PMINTENSET_EL1 == 0) */ > > mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E); > report(expect_interrupts(0), "no overflow interrupt after preset"); > @@ -841,7 +841,7 @@ static void test_overflow_interrupt(void) > isb(); > report(expect_interrupts(0), "no overflow interrupt after counting"); > > - /* enable interrupts */ > + /* enable interrupts (PMINTENSET_EL1 <= ALL_SET) */ > > pmu_reset_stats(); > > @@ -889,6 +889,7 @@ static bool check_cycles_increase(void) > bool success = true; > > /* init before event access, this test only cares about cycle count */ > + pmu_reset(); > set_pmcntenset(1 << PMU_CYCLE_IDX); > set_pmccfiltr(0); /* count cycles in EL0, EL1, but not EL2 */ > > @@ -943,6 +944,7 @@ static bool check_cpi(int cpi) > uint32_t pmcr = get_pmcr() | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_E; > > /* init before event access, this test only cares about cycle count */ > + pmu_reset(); > set_pmcntenset(1 << PMU_CYCLE_IDX); > set_pmccfiltr(0); /* count cycles in EL0, EL1, but not EL2 */ >
diff --git a/arm/pmu.c b/arm/pmu.c index 76156f78..7c5bc259 100644 --- a/arm/pmu.c +++ b/arm/pmu.c @@ -826,7 +826,7 @@ static void test_overflow_interrupt(void) write_regn_el0(pmevcntr, 1, PRE_OVERFLOW); isb(); - /* interrupts are disabled */ + /* interrupts are disabled (PMINTENSET_EL1 == 0) */ mem_access_loop(addr, 200, pmu.pmcr_ro | PMU_PMCR_E); report(expect_interrupts(0), "no overflow interrupt after preset"); @@ -841,7 +841,7 @@ static void test_overflow_interrupt(void) isb(); report(expect_interrupts(0), "no overflow interrupt after counting"); - /* enable interrupts */ + /* enable interrupts (PMINTENSET_EL1 <= ALL_SET) */ pmu_reset_stats(); @@ -889,6 +889,7 @@ static bool check_cycles_increase(void) bool success = true; /* init before event access, this test only cares about cycle count */ + pmu_reset(); set_pmcntenset(1 << PMU_CYCLE_IDX); set_pmccfiltr(0); /* count cycles in EL0, EL1, but not EL2 */ @@ -943,6 +944,7 @@ static bool check_cpi(int cpi) uint32_t pmcr = get_pmcr() | PMU_PMCR_LC | PMU_PMCR_C | PMU_PMCR_E; /* init before event access, this test only cares about cycle count */ + pmu_reset(); set_pmcntenset(1 << PMU_CYCLE_IDX); set_pmccfiltr(0); /* count cycles in EL0, EL1, but not EL2 */
Some registers like the PMOVS reset to an architecturally UNKNOWN value. Most tests expect them to be reset (mostly zeroed) using pmu_reset(). Add a pmu_reset() on all the tests that need one. As a bonus, fix a couple of comments related to the register state before a sub-test. Signed-off-by: Ricardo Koller <ricarkol@google.com> --- arm/pmu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)