| Message ID | 20220720213036.1738628-4-Frank.Li@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3,1/4] irqchip: allow pass down .pm field at IRQCHIP_PLATFORM_DRIVER_END | expand |
On 20/07/2022 23:30, Frank Li wrote: > imx mu support generate irq by write a register. > provide msi controller support so other driver > can use it by standard msi interface. Please start sentences with capital letter. Unfortunately I don't understand the sentences. Please describe shortly the hardware. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > .../interrupt-controller/fsl,mu-msi.yaml | 88 +++++++++++++++++++ > 1 file changed, 88 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml > new file mode 100644 > index 0000000000000..e125294243af3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml > @@ -0,0 +1,88 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP i.MX Messaging Unit (MU) work as msi controller > + > +maintainers: > + - Frank Li <Frank.Li@nxp.com> > + > +description: | > + The Messaging Unit module enables two processors within the SoC to > + communicate and coordinate by passing messages (e.g. data, status > + and control) through the MU interface. The MU also provides the ability > + for one processor to signal the other processor using interrupts. > + > + Because the MU manages the messaging between processors, the MU uses > + different clocks (from each side of the different peripheral buses). > + Therefore, the MU must synchronize the accesses from one side to the > + other. The MU accomplishes synchronization using two sets of matching > + registers (Processor A-facing, Processor B-facing). > + > + MU can work as msi interrupt controller to do doorbell > + > +allOf: > + - $ref: /schemas/interrupt-controller/msi-controller.yaml# > + > +properties: > + compatible: > + enum: > + - fsl,imx6sx-mu-msi > + - fsl,imx7ulp-mu-msi > + - fsl,imx8ulp-mu-msi > + - fsl,imx8ulp-mu-msi-s4 > + > + reg: > + minItems: 2 Not minItems but maxItems in general, but anyway you need to actually list and describe the items (and then skip min/max) > + > + reg-names: > + items: > + - const: a > + - const: b > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + power-domains: > + maxItems: 2 and here you correctly use maxItems, so why min in reg? Anyway, instead you need to list and describe the items. Actually I asked you this last time about interrupts, so you ignored that comment. > + > + power-domain-names: > + items: > + - const: a > + - const: b > + > + interrupt-controller: true > + > + msi-controller: true > + > +required: > + - compatible > + - reg > + - interrupts > + - msi-controller > + - interrupt-controller Why different order than used in properties? Best regards, Krzysztof
> -----Original Message----- > From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Sent: Saturday, July 23, 2022 1:50 PM > To: Frank Li <frank.li@nxp.com>; jdmason@kudzu.us; maz@kernel.org; > tglx@linutronix.de; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > shawnguo@kernel.org; s.hauer@pengutronix.de; kw@linux.com; > bhelgaas@google.com > Cc: kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-pci@vger.kernel.org; Peng Fan > <peng.fan@nxp.com>; Aisheng Dong <aisheng.dong@nxp.com>; > kernel@pengutronix.de; festevam@gmail.com; dl-linux-imx <linux- > imx@nxp.com>; kishon@ti.com; lorenzo.pieralisi@arm.com; > ntb@lists.linux.dev > Subject: [EXT] Re: [PATCH v3 3/4] dt-bindings: irqchip: imx mu work as msi > controller > > Caution: EXT Email > > On 20/07/2022 23:30, Frank Li wrote: > > imx mu support generate irq by write a register. > > provide msi controller support so other driver > > can use it by standard msi interface. > > Please start sentences with capital letter. Unfortunately I don't > understand the sentences. Please describe shortly the hardware. [Frank Li] MU have 4 registers and both side A and B. If write one of Register, irq will be trigger at the other side. For example, writle(a side reg1, 0). Then b side irq will be trigged. > > > > > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > .../interrupt-controller/fsl,mu-msi.yaml | 88 +++++++++++++++++++ > > 1 file changed, 88 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/interrupt- > controller/fsl,mu-msi.yaml > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,mu- > msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu- > msi.yaml > > new file mode 100644 > > index 0000000000000..e125294243af3 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu- > msi.yaml > > @@ -0,0 +1,88 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicet > ree.org%2Fschemas%2Finterrupt-controller%2Ffsl%2Cmu- > msi.yaml%23&data=05%7C01%7CFrank.Li%40nxp.com%7Cfcec12a0731c > 454af5c308da6cdc2a0e%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0 > %7C637941990101591376%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLj > AwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C% > 7C%7C&sdata=9h9nKyvsWaghry1hkpa5aaxVGYpx6xZRTxhN0S4uB50%3 > D&reserved=0 > > +$schema: > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicet > ree.org%2Fmeta- > schemas%2Fcore.yaml%23&data=05%7C01%7CFrank.Li%40nxp.com%7 > Cfcec12a0731c454af5c308da6cdc2a0e%7C686ea1d3bc2b4c6fa92cd99c5c3016 > 35%7C0%7C0%7C637941990101591376%7CUnknown%7CTWFpbGZsb3d8eyJ > WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D% > 7C3000%7C%7C%7C&sdata=wagM3hl8fpJSm%2Bibw6ENl5lNlQ9fVEHzS > OlT%2Bjoridg%3D&reserved=0 > > + > > +title: NXP i.MX Messaging Unit (MU) work as msi controller > > + > > +maintainers: > > + - Frank Li <Frank.Li@nxp.com> > > + > > +description: | > > + The Messaging Unit module enables two processors within the SoC to > > + communicate and coordinate by passing messages (e.g. data, status > > + and control) through the MU interface. The MU also provides the ability > > + for one processor to signal the other processor using interrupts. > > + > > + Because the MU manages the messaging between processors, the MU > uses > > + different clocks (from each side of the different peripheral buses). > > + Therefore, the MU must synchronize the accesses from one side to the > > + other. The MU accomplishes synchronization using two sets of matching > > + registers (Processor A-facing, Processor B-facing). > > + > > + MU can work as msi interrupt controller to do doorbell > > + > > +allOf: > > + - $ref: /schemas/interrupt-controller/msi-controller.yaml# > > + > > +properties: > > + compatible: > > + enum: > > + - fsl,imx6sx-mu-msi > > + - fsl,imx7ulp-mu-msi > > + - fsl,imx8ulp-mu-msi > > + - fsl,imx8ulp-mu-msi-s4 > > + > > + reg: > > + minItems: 2 > > Not minItems but maxItems in general, but anyway you need to actually > list and describe the items (and then skip min/max) [Frank Li] I am not sure format. Any example? Reg: Items: - description: a side register - description: b side register > > > + > > + reg-names: > > + items: > > + - const: a > > + - const: b > > + > > + interrupts: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + power-domains: > > + maxItems: 2 > > and here you correctly use maxItems, so why min in reg? Anyway, instead > you need to list and describe the items. Does format is similar with reg? > > Actually I asked you this last time about interrupts, so you ignored > that comment. Sorry, which one. Is it below one? --- > + interrupts: > + minItems: 1 > + maxItems: 2 Instead describe the items. --- > > > + > > + power-domain-names: > > + items: > > + - const: a > > + - const: b > > + > > + interrupt-controller: true > > + > > + msi-controller: true > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - msi-controller > > + - interrupt-controller > > Why different order than used in properties? > > > > Best regards, > Krzysztof
On 25/07/2022 18:29, Frank Li wrote: > > >> -----Original Message----- >> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> Sent: Saturday, July 23, 2022 1:50 PM >> To: Frank Li <frank.li@nxp.com>; jdmason@kudzu.us; maz@kernel.org; >> tglx@linutronix.de; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; >> shawnguo@kernel.org; s.hauer@pengutronix.de; kw@linux.com; >> bhelgaas@google.com >> Cc: kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-arm- >> kernel@lists.infradead.org; linux-pci@vger.kernel.org; Peng Fan >> <peng.fan@nxp.com>; Aisheng Dong <aisheng.dong@nxp.com>; >> kernel@pengutronix.de; festevam@gmail.com; dl-linux-imx <linux- >> imx@nxp.com>; kishon@ti.com; lorenzo.pieralisi@arm.com; >> ntb@lists.linux.dev >> Subject: [EXT] Re: [PATCH v3 3/4] dt-bindings: irqchip: imx mu work as msi >> controller >> >> Caution: EXT Email >> >> On 20/07/2022 23:30, Frank Li wrote: >>> imx mu support generate irq by write a register. >>> provide msi controller support so other driver >>> can use it by standard msi interface. >> >> Please start sentences with capital letter. Unfortunately I don't >> understand the sentences. Please describe shortly the hardware. > > [Frank Li] MU have 4 registers and both side A and B. If write one of > Register, irq will be trigger at the other side. > > For example, writle(a side reg1, 0). Then b side irq will be trigged. > >> >> >>> >>> Signed-off-by: Frank Li <Frank.Li@nxp.com> >>> --- >>> .../interrupt-controller/fsl,mu-msi.yaml | 88 +++++++++++++++++++ >>> 1 file changed, 88 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/interrupt- >> controller/fsl,mu-msi.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,mu- >> msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu- >> msi.yaml >>> new file mode 100644 >>> index 0000000000000..e125294243af3 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu- >> msi.yaml >>> @@ -0,0 +1,88 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +%YAML 1.2 >>> +--- >>> +$id: >> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicet >> ree.org%2Fschemas%2Finterrupt-controller%2Ffsl%2Cmu- >> msi.yaml%23&data=05%7C01%7CFrank.Li%40nxp.com%7Cfcec12a0731c >> 454af5c308da6cdc2a0e%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0 >> %7C637941990101591376%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLj >> AwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C% >> 7C%7C&sdata=9h9nKyvsWaghry1hkpa5aaxVGYpx6xZRTxhN0S4uB50%3 >> D&reserved=0 >>> +$schema: >> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicet >> ree.org%2Fmeta- >> schemas%2Fcore.yaml%23&data=05%7C01%7CFrank.Li%40nxp.com%7 >> Cfcec12a0731c454af5c308da6cdc2a0e%7C686ea1d3bc2b4c6fa92cd99c5c3016 >> 35%7C0%7C0%7C637941990101591376%7CUnknown%7CTWFpbGZsb3d8eyJ >> WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D% >> 7C3000%7C%7C%7C&sdata=wagM3hl8fpJSm%2Bibw6ENl5lNlQ9fVEHzS >> OlT%2Bjoridg%3D&reserved=0 >>> + >>> +title: NXP i.MX Messaging Unit (MU) work as msi controller >>> + >>> +maintainers: >>> + - Frank Li <Frank.Li@nxp.com> >>> + >>> +description: | >>> + The Messaging Unit module enables two processors within the SoC to >>> + communicate and coordinate by passing messages (e.g. data, status >>> + and control) through the MU interface. The MU also provides the ability >>> + for one processor to signal the other processor using interrupts. >>> + >>> + Because the MU manages the messaging between processors, the MU >> uses >>> + different clocks (from each side of the different peripheral buses). >>> + Therefore, the MU must synchronize the accesses from one side to the >>> + other. The MU accomplishes synchronization using two sets of matching >>> + registers (Processor A-facing, Processor B-facing). >>> + >>> + MU can work as msi interrupt controller to do doorbell >>> + >>> +allOf: >>> + - $ref: /schemas/interrupt-controller/msi-controller.yaml# >>> + >>> +properties: >>> + compatible: >>> + enum: >>> + - fsl,imx6sx-mu-msi >>> + - fsl,imx7ulp-mu-msi >>> + - fsl,imx8ulp-mu-msi >>> + - fsl,imx8ulp-mu-msi-s4 >>> + >>> + reg: >>> + minItems: 2 >> >> Not minItems but maxItems in general, but anyway you need to actually >> list and describe the items (and then skip min/max) > [Frank Li] > I am not sure format. Any example? > > Reg: > Items: > - description: a side register > - description: b side register Yes, but then explain what is A and B in bindings description. Why MU, which sits on A side needs to access other side (B) registers? >> >>> + >>> + reg-names: >>> + items: >>> + - const: a >>> + - const: b >>> + >>> + interrupts: >>> + maxItems: 1 >>> + >>> + clocks: >>> + maxItems: 1 >>> + >>> + power-domains: >>> + maxItems: 2 >> >> and here you correctly use maxItems, so why min in reg? Anyway, instead >> you need to list and describe the items. > > Does format is similar with reg? Yes. > >> >> Actually I asked you this last time about interrupts, so you ignored >> that comment. > > Sorry, which one. Is it below one? > > --- >> + interrupts: >> + minItems: 1 >> + maxItems: 2 > > Instead describe the items. Yes. Best regards, Krzysztof
> -----Original Message----- > From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Sent: Monday, July 25, 2022 11:45 AM > To: Frank Li <frank.li@nxp.com>; jdmason@kudzu.us; maz@kernel.org; > tglx@linutronix.de; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > shawnguo@kernel.org; s.hauer@pengutronix.de; kw@linux.com; > bhelgaas@google.com > Cc: kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-pci@vger.kernel.org; Peng Fan > <peng.fan@nxp.com>; Aisheng Dong <aisheng.dong@nxp.com>; > kernel@pengutronix.de; festevam@gmail.com; dl-linux-imx <linux- > imx@nxp.com>; kishon@ti.com; lorenzo.pieralisi@arm.com; > ntb@lists.linux.dev > Subject: Re: [EXT] Re: [PATCH v3 3/4] dt-bindings: irqchip: imx mu work as > msi controller > > Caution: EXT Email > > On 25/07/2022 18:29, Frank Li wrote: > > > > > >> -----Original Message----- > >> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > >> Sent: Saturday, July 23, 2022 1:50 PM > >> To: Frank Li <frank.li@nxp.com>; jdmason@kudzu.us; maz@kernel.org; > >> tglx@linutronix.de; robh+dt@kernel.org; > krzysztof.kozlowski+dt@linaro.org; > >> shawnguo@kernel.org; s.hauer@pengutronix.de; kw@linux.com; > >> bhelgaas@google.com > >> Cc: kernel@vger.kernel.org; devicetree@vger.kernel.org; linux-arm- > >> kernel@lists.infradead.org; linux-pci@vger.kernel.org; Peng Fan > >> <peng.fan@nxp.com>; Aisheng Dong <aisheng.dong@nxp.com>; > >> kernel@pengutronix.de; festevam@gmail.com; dl-linux-imx <linux- > >> imx@nxp.com>; kishon@ti.com; lorenzo.pieralisi@arm.com; > >> ntb@lists.linux.dev > >> Subject: [EXT] Re: [PATCH v3 3/4] dt-bindings: irqchip: imx mu work as msi > >> controller > >> > >> Caution: EXT Email > >> > >> On 20/07/2022 23:30, Frank Li wrote: > >>> imx mu support generate irq by write a register. > >>> provide msi controller support so other driver > >>> can use it by standard msi interface. > >> > >> Please start sentences with capital letter. Unfortunately I don't > >> understand the sentences. Please describe shortly the hardware. > > > > [Frank Li] MU have 4 registers and both side A and B. If write one of > > Register, irq will be trigger at the other side. > > > > For example, writle(a side reg1, 0). Then b side irq will be trigged. > > > > > > >> > >> > >>> > >>> Signed-off-by: Frank Li <Frank.Li@nxp.com> > >>> --- > >>> .../interrupt-controller/fsl,mu-msi.yaml | 88 +++++++++++++++++++ > >>> 1 file changed, 88 insertions(+) > >>> create mode 100644 Documentation/devicetree/bindings/interrupt- > >> controller/fsl,mu-msi.yaml > >>> > >>> diff --git a/Documentation/devicetree/bindings/interrupt- > controller/fsl,mu- > >> msi.yaml b/Documentation/devicetree/bindings/interrupt- > controller/fsl,mu- > >> msi.yaml > >>> new file mode 100644 > >>> index 0000000000000..e125294243af3 > >>> --- /dev/null > >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu- > >> msi.yaml > >>> @@ -0,0 +1,88 @@ > >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > >>> +%YAML 1.2 > >>> +--- > >>> +$id: > >> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicet > >> ree.org%2Fschemas%2Finterrupt-controller%2Ffsl%2Cmu- > >> > msi.yaml%23&data=05%7C01%7CFrank.Li%40nxp.com%7Cfcec12a0731c > >> > 454af5c308da6cdc2a0e%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0 > >> %7C637941990101591376%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4 > wLj > >> > AwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C% > >> > 7C%7C&sdata=9h9nKyvsWaghry1hkpa5aaxVGYpx6xZRTxhN0S4uB50%3 > >> D&reserved=0 > >>> +$schema: > >> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicet > >> ree.org%2Fmeta- > >> > schemas%2Fcore.yaml%23&data=05%7C01%7CFrank.Li%40nxp.com%7 > >> > Cfcec12a0731c454af5c308da6cdc2a0e%7C686ea1d3bc2b4c6fa92cd99c5c3016 > >> > 35%7C0%7C0%7C637941990101591376%7CUnknown%7CTWFpbGZsb3d8eyJ > >> > WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D% > >> > 7C3000%7C%7C%7C&sdata=wagM3hl8fpJSm%2Bibw6ENl5lNlQ9fVEHzS > >> OlT%2Bjoridg%3D&reserved=0 > >>> + > >>> +title: NXP i.MX Messaging Unit (MU) work as msi controller > >>> + > >>> +maintainers: > >>> + - Frank Li <Frank.Li@nxp.com> > >>> + > >>> +description: | > >>> + The Messaging Unit module enables two processors within the SoC to > >>> + communicate and coordinate by passing messages (e.g. data, status > >>> + and control) through the MU interface. The MU also provides the > ability > >>> + for one processor to signal the other processor using interrupts. > >>> + > >>> + Because the MU manages the messaging between processors, the MU > >> uses > >>> + different clocks (from each side of the different peripheral buses). > >>> + Therefore, the MU must synchronize the accesses from one side to the > >>> + other. The MU accomplishes synchronization using two sets of > matching > >>> + registers (Processor A-facing, Processor B-facing). > >>> + > >>> + MU can work as msi interrupt controller to do doorbell > >>> + > >>> +allOf: > >>> + - $ref: /schemas/interrupt-controller/msi-controller.yaml# > >>> + > >>> +properties: > >>> + compatible: > >>> + enum: > >>> + - fsl,imx6sx-mu-msi > >>> + - fsl,imx7ulp-mu-msi > >>> + - fsl,imx8ulp-mu-msi > >>> + - fsl,imx8ulp-mu-msi-s4 > >>> + > >>> + reg: > >>> + minItems: 2 > >> > >> Not minItems but maxItems in general, but anyway you need to actually > >> list and describe the items (and then skip min/max) > > [Frank Li] > > I am not sure format. Any example? > > > > Reg: > > Items: > > - description: a side register > > - description: b side register > > Yes, but then explain what is A and B in bindings description. [Frank Li] How about "A(B) side base register address." Any other description need? > > Why MU, which sits on A side needs to access other side (B) registers? [Frank Li] MU work as MSI controller for PCI EP. So driver need provide B side register to PCI EP by msi_msg. PCI EP driver use this address to set PCI bar<n>. Then PCI host can write this address to trigger PCIe EP side irq As doorbell. MU MSI driver also need A side register To get irq status. So MU MSI need both side registers. > > >> > >>> + > >>> + reg-names: > >>> + items: > >>> + - const: a > >>> + - const: b > >>> + > >>> + interrupts: > >>> + maxItems: 1 > >>> + > >>> + clocks: > >>> + maxItems: 1 > >>> + > >>> + power-domains: > >>> + maxItems: 2 > >> > >> and here you correctly use maxItems, so why min in reg? Anyway, instead > >> you need to list and describe the items. > > > > Does format is similar with reg? > > Yes. > > > > >> > >> Actually I asked you this last time about interrupts, so you ignored > >> that comment. > > > > Sorry, which one. Is it below one? > > > > --- > >> + interrupts: > >> + minItems: 1 > >> + maxItems: 2 > > > > Instead describe the items. > > Yes. > > > Best regards, > Krzysztof
On 25/07/2022 18:55, Frank Li wrote: >>>> Not minItems but maxItems in general, but anyway you need to actually >>>> list and describe the items (and then skip min/max) >>> [Frank Li] >>> I am not sure format. Any example? >>> >>> Reg: >>> Items: >>> - description: a side register >>> - description: b side register >> >> Yes, but then explain what is A and B in bindings description. > > [Frank Li] How about "A(B) side base register address." > Any other description need? In top-level description you have: "The MU also provides the ability for one processor to signal the other processor using interrupts." so maybe: "The MU also provides the ability for one processor (A side) to signal the other processor (B side) using interrupts." > >> >> Why MU, which sits on A side needs to access other side (B) registers? > > [Frank Li] MU work as MSI controller for PCI EP. So driver need provide > B side register to PCI EP by msi_msg. PCI EP driver use this address to set > PCI bar<n>. Then PCI host can write this address to trigger PCIe EP side irq > As doorbell. > > MU MSI driver also need A side register > To get irq status. So MU MSI need both side registers. OK. Best regards, Krzysztof
On Wed, Jul 20, 2022 at 3:31 PM Frank Li <Frank.Li@nxp.com> wrote: > > imx mu support generate irq by write a register. > provide msi controller support so other driver > can use it by standard msi interface. > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > --- > .../interrupt-controller/fsl,mu-msi.yaml | 88 +++++++++++++++++++ > 1 file changed, 88 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml This is failing in linux-next now, but I'm wondering why it is there given all the comments. Error: Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.example.dts:31.41-42 syntax error FATAL ERROR: Unable to parse input tree make[1]: *** [scripts/Makefile.lib:396: Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.example.dtb] Error 1 Rob
On 2022-08-10 15:01, Rob Herring wrote: > On Wed, Jul 20, 2022 at 3:31 PM Frank Li <Frank.Li@nxp.com> wrote: >> >> imx mu support generate irq by write a register. >> provide msi controller support so other driver >> can use it by standard msi interface. >> >> Signed-off-by: Frank Li <Frank.Li@nxp.com> >> --- >> .../interrupt-controller/fsl,mu-msi.yaml | 88 >> +++++++++++++++++++ >> 1 file changed, 88 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml > > This is failing in linux-next now, but I'm wondering why it is there > given all the comments. *BLINK* Jon, please drop this and the corresponding irqchip changes from -next. There is definitely not 6.1 material if the current code is anything to go by. That'd be commits: 621b7555c914 ("dt-bindings: irqchip: imx mu work as msi controller") 893ae515ff8d ("irqchip: imx mu worked as msi controller") Once it is ready, I'll take it via the irqchip tree. But only when it is ready. Thanks, M.
On Wed, Aug 10, 2022 at 08:01:29AM -0600, Rob Herring wrote: > On Wed, Jul 20, 2022 at 3:31 PM Frank Li <Frank.Li@nxp.com> wrote: > > > > imx mu support generate irq by write a register. > > provide msi controller support so other driver > > can use it by standard msi interface. > > > > Signed-off-by: Frank Li <Frank.Li@nxp.com> > > --- > > .../interrupt-controller/fsl,mu-msi.yaml | 88 +++++++++++++++++++ > > 1 file changed, 88 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml > > This is failing in linux-next now, but I'm wondering why it is there > given all the comments. That was my fault. It is gone now. I was trying to get caught up with patches, applied everything in my inbox to ntb-next, and was pulling stuff out when it synced (cronjob backup of all git trees to github). Sorry, Jon > > Error: Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.example.dts:31.41-42 > syntax error > FATAL ERROR: Unable to parse input tree > make[1]: *** [scripts/Makefile.lib:396: > Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.example.dtb] > Error 1 > > Rob
diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml new file mode 100644 index 0000000000000..e125294243af3 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX Messaging Unit (MU) work as msi controller + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: | + The Messaging Unit module enables two processors within the SoC to + communicate and coordinate by passing messages (e.g. data, status + and control) through the MU interface. The MU also provides the ability + for one processor to signal the other processor using interrupts. + + Because the MU manages the messaging between processors, the MU uses + different clocks (from each side of the different peripheral buses). + Therefore, the MU must synchronize the accesses from one side to the + other. The MU accomplishes synchronization using two sets of matching + registers (Processor A-facing, Processor B-facing). + + MU can work as msi interrupt controller to do doorbell + +allOf: + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + enum: + - fsl,imx6sx-mu-msi + - fsl,imx7ulp-mu-msi + - fsl,imx8ulp-mu-msi + - fsl,imx8ulp-mu-msi-s4 + + reg: + minItems: 2 + + reg-names: + items: + - const: a + - const: b + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 2 + + power-domain-names: + items: + - const: a + - const: b + + interrupt-controller: true + + msi-controller: true + +required: + - compatible + - reg + - interrupts + - msi-controller + - interrupt-controller + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/firmware/imx/rsrc.h> + + lsio_mu12: msi-controller@5d270000 { + compatible = "fsl,imx6sx-mu-msi"; + msi-controller; + interrupt-controller; + reg = <0x5d270000 0x10000>, /* A side */ + <0x5d300000 0x10000>; /* B side */ + reg-names = "a", "b"; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd IMX_SC_R_MU_12A>, + <&pd IMX_SC_R_MU_12B>; + power-domain-names = "a", "b"; + };
imx mu support generate irq by write a register. provide msi controller support so other driver can use it by standard msi interface. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- .../interrupt-controller/fsl,mu-msi.yaml | 88 +++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml