| Message ID | 166026184968.1454405.494690416353090765.stgit@djiang5-desk4.jf.intel.com |
|---|---|
| Headers | show |
| Series | Add sanity check for interleave setup | expand |
Dave Jiang wrote: > The small series adds sanity check for the combination of interleave ways > and interleave granularity during region and port configuration. The > calculation references CXL spec 3.0 8.2.4.19.13 implementation note #3. The > checks also added HDM CAP retrieval for the support of new interleave ways > where 3, 6, and 12 ways support as well as 16 ways support. > > v2: > - Change cxl_interleave_verify() to cxl_interleave_capable(). (Dan) > - Move error output inside verify function. (Dan) > - Remove unneeded enums. (Dan) > - Use is_power_of_2() to detect encoded interleave ways. (Dan) > - Change iw to eiw and ig to eig for encoded values. (Alison) > - Change interleave capabilities to mask for easier comparison. (Dan) > - Change valid_interleave() to valid_interleave_ways() > - Add setting fo interleave_cap to cxl_test. (Dan) > > --- > > Dave Jiang (3): > cxl: Add check for result of interleave ways plus granularity combo > cxl: Add CXL spec v3.0 interleave support > tools/testing/cxl: Add interleave check support to mock cxl port device After reviewing Vishal's create-region series, I think this patch-kit wants one more patch in the next posting, or as a follow-on. Add 'interleave_mask' and 'interleave_cap' as new port sysfs attributes. Likely they need to be added to cxl_port_attribute_groups since they are only valid while the cxl_port driver is attached.
The small series adds sanity check for the combination of interleave ways and interleave granularity during region and port configuration. The calculation references CXL spec 3.0 8.2.4.19.13 implementation note #3. The checks also added HDM CAP retrieval for the support of new interleave ways where 3, 6, and 12 ways support as well as 16 ways support. v2: - Change cxl_interleave_verify() to cxl_interleave_capable(). (Dan) - Move error output inside verify function. (Dan) - Remove unneeded enums. (Dan) - Use is_power_of_2() to detect encoded interleave ways. (Dan) - Change iw to eiw and ig to eig for encoded values. (Alison) - Change interleave capabilities to mask for easier comparison. (Dan) - Change valid_interleave() to valid_interleave_ways() - Add setting fo interleave_cap to cxl_test. (Dan) --- Dave Jiang (3): cxl: Add check for result of interleave ways plus granularity combo cxl: Add CXL spec v3.0 interleave support tools/testing/cxl: Add interleave check support to mock cxl port device drivers/cxl/core/hdm.c | 6 +++++ drivers/cxl/core/region.c | 11 +++++++- drivers/cxl/cxl.h | 2 ++ drivers/cxl/cxlmem.h | 50 ++++++++++++++++++++++++++++++++++++ tools/testing/cxl/test/cxl.c | 3 +++ 5 files changed, 71 insertions(+), 1 deletion(-) --