| Message ID | 20220817095629.29911-3-moudy.ho@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | media: mediatek: support mdp3 on mt8183 platform | expand |
On 17/08/2022 11:56, Moudy Ho wrote: > This patch adds DT binding documentation for MediaTek's CCORR and > WDMA components. > These components exist in both MediaTek's Media Data Path 3(MDP3) and DRM, > and the bindings are placed under the folder "./soc/mediatek" to prevent > duplicate builds. > > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> > Reviewed-by: Rob Herring <robh@kernel.org> > Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > .../bindings/soc/mediatek/mediatek,ccorr.yaml | 68 ++++++++++++++++ > .../bindings/soc/mediatek/mediatek,wdma.yaml | 81 +++++++++++++++++++ > 2 files changed, 149 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml > create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > > diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml > new file mode 100644 > index 000000000000..10786d769750 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml > @@ -0,0 +1,68 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek color correction > + > +maintainers: > + - Matthias Brugger <matthias.bgg@gmail.com> > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com> Same here. Regards, Matthias > + > +description: | > + MediaTek color correction with 3X3 matrix. > + > +properties: > + compatible: > + items: > + - enum: > + - mediatek,mt8183-mdp3-ccorr > + > + reg: > + maxItems: 1 > + > + mediatek,gce-client-reg: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + items: > + - description: phandle of GCE > + - description: GCE subsys id > + - description: register offset > + - description: register size > + description: The register of client driver can be configured by gce with > + 4 arguments defined in this property. Each GCE subsys id is mapping to > + a client defined in the header include/dt-bindings/gce/<chip>-gce.h. > + > + mediatek,gce-events: > + description: > + The event id which is mapping to the specific hardware event signal > + to gce. The event id is defined in the gce header > + include/dt-bindings/gce/<chip>-gce.h of each chips. > + $ref: /schemas/types.yaml#/definitions/uint32-array > + > + clocks: > + minItems: 1 > + > +required: > + - compatible > + - reg > + - mediatek,gce-client-reg > + - mediatek,gce-events > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/mt8183-clk.h> > + #include <dt-bindings/gce/mt8183-gce.h> > + > + mdp3_ccorr: mdp3-ccorr@1401c000 { > + compatible = "mediatek,mt8183-mdp3-ccorr"; > + reg = <0x1401c000 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>; > + mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>, > + <CMDQ_EVENT_MDP_CCORR_EOF>; > + clocks = <&mmsys CLK_MM_MDP_CCORR>; > + }; > diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > new file mode 100644 > index 000000000000..95ec19543945 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > @@ -0,0 +1,81 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,wdma.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Write Direct Memory Access > + > +maintainers: > + - Matthias Brugger <matthias.bgg@gmail.com> > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com> > + > +description: | > + MediaTek Write Direct Memory Access(WDMA) component used to write > + the data into DMA. > + > +properties: > + compatible: > + items: > + - enum: > + - mediatek,mt8183-mdp3-wdma > + > + reg: > + maxItems: 1 > + > + mediatek,gce-client-reg: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + items: > + - description: phandle of GCE > + - description: GCE subsys id > + - description: register offset > + - description: register size > + description: The register of client driver can be configured by gce with > + 4 arguments defined in this property. Each GCE subsys id is mapping to > + a client defined in the header include/dt-bindings/gce/<chip>-gce.h. > + > + mediatek,gce-events: > + description: > + The event id which is mapping to the specific hardware event signal > + to gce. The event id is defined in the gce header > + include/dt-bindings/gce/<chip>-gce.h of each chips. > + $ref: /schemas/types.yaml#/definitions/uint32-array > + > + power-domains: > + maxItems: 1 > + > + clocks: > + minItems: 1 > + > + iommus: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - mediatek,gce-client-reg > + - mediatek,gce-events > + - power-domains > + - clocks > + - iommus > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/mt8183-clk.h> > + #include <dt-bindings/gce/mt8183-gce.h> > + #include <dt-bindings/power/mt8183-power.h> > + #include <dt-bindings/memory/mt8183-larb-port.h> > + > + mdp3_wdma: mdp3-wdma@14006000 { > + compatible = "mediatek,mt8183-mdp3-wdma"; > + reg = <0x14006000 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; > + mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>, > + <CMDQ_EVENT_MDP_WDMA0_EOF>; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_MDP_WDMA0>; > + iommus = <&iommu>; > + };
Hi Matthias, On Mon, 2022-08-22 at 16:32 +0200, Matthias Brugger wrote: > > On 17/08/2022 11:56, Moudy Ho wrote: > > This patch adds DT binding documentation for MediaTek's CCORR and > > WDMA components. > > These components exist in both MediaTek's Media Data Path 3(MDP3) > > and DRM, > > and the bindings are placed under the folder "./soc/mediatek" to > > prevent > > duplicate builds. > > > > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> > > Reviewed-by: Rob Herring <robh@kernel.org> > > Reviewed-by: AngeloGioacchino Del Regno < > > angelogioacchino.delregno@collabora.com> > > --- > > .../bindings/soc/mediatek/mediatek,ccorr.yaml | 68 > > ++++++++++++++++ > > .../bindings/soc/mediatek/mediatek,wdma.yaml | 81 > > +++++++++++++++++++ > > 2 files changed, 149 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml > > create mode 100644 > > Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yam > > l > > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yam > > l > > new file mode 100644 > > index 000000000000..10786d769750 > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yam > > l > > @@ -0,0 +1,68 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml*__;Iw!!CTRNKA9wMg0ARbw!3h7qYnjiwvN90iwxMZCIpxo-QWZqllWu4mMpB6NSjDHPKnuM4mITblmweAeVniXJ$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!3h7qYnjiwvN90iwxMZCIpxo-QWZqllWu4mMpB6NSjDHPKnuM4mITblmweCOWt0j9$ > > > > + > > +title: MediaTek color correction > > + > > +maintainers: > > + - Matthias Brugger <matthias.bgg@gmail.com> > > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com> > > Same here. > > Regards, > Matthias > Thanks for the reminder, I'll deal with it together with the previous patch Regards, Moudy > > + > > +description: | > > + MediaTek color correction with 3X3 matrix. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - mediatek,mt8183-mdp3-ccorr > > + > > + reg: > > + maxItems: 1 > > + > > + mediatek,gce-client-reg: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + items: > > + items: > > + - description: phandle of GCE > > + - description: GCE subsys id > > + - description: register offset > > + - description: register size > > + description: The register of client driver can be configured > > by gce with > > + 4 arguments defined in this property. Each GCE subsys id is > > mapping to > > + a client defined in the header include/dt- > > bindings/gce/<chip>-gce.h. > > + > > + mediatek,gce-events: > > + description: > > + The event id which is mapping to the specific hardware event > > signal > > + to gce. The event id is defined in the gce header > > + include/dt-bindings/gce/<chip>-gce.h of each chips. > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > + > > + clocks: > > + minItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - mediatek,gce-client-reg > > + - mediatek,gce-events > > + - clocks > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/mt8183-clk.h> > > + #include <dt-bindings/gce/mt8183-gce.h> > > + > > + mdp3_ccorr: mdp3-ccorr@1401c000 { > > + compatible = "mediatek,mt8183-mdp3-ccorr"; > > + reg = <0x1401c000 0x1000>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 > > 0x1000>; > > + mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>, > > + <CMDQ_EVENT_MDP_CCORR_EOF>; > > + clocks = <&mmsys CLK_MM_MDP_CCORR>; > > + }; > > diff --git > > a/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > > new file mode 100644 > > index 000000000000..95ec19543945 > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml > > @@ -0,0 +1,81 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/soc/mediatek/mediatek,wdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!3h7qYnjiwvN90iwxMZCIpxo-QWZqllWu4mMpB6NSjDHPKnuM4mITblmweNEpTeKs$ > > > > +$schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!3h7qYnjiwvN90iwxMZCIpxo-QWZqllWu4mMpB6NSjDHPKnuM4mITblmweCOWt0j9$ > > > > + > > +title: MediaTek Write Direct Memory Access > > + > > +maintainers: > > + - Matthias Brugger <matthias.bgg@gmail.com> > > + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com> > > + > > +description: | > > + MediaTek Write Direct Memory Access(WDMA) component used to > > write > > + the data into DMA. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + - mediatek,mt8183-mdp3-wdma > > + > > + reg: > > + maxItems: 1 > > + > > + mediatek,gce-client-reg: > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + items: > > + items: > > + - description: phandle of GCE > > + - description: GCE subsys id > > + - description: register offset > > + - description: register size > > + description: The register of client driver can be configured > > by gce with > > + 4 arguments defined in this property. Each GCE subsys id is > > mapping to > > + a client defined in the header include/dt- > > bindings/gce/<chip>-gce.h. > > + > > + mediatek,gce-events: > > + description: > > + The event id which is mapping to the specific hardware event > > signal > > + to gce. The event id is defined in the gce header > > + include/dt-bindings/gce/<chip>-gce.h of each chips. > > + $ref: /schemas/types.yaml#/definitions/uint32-array > > + > > + power-domains: > > + maxItems: 1 > > + > > + clocks: > > + minItems: 1 > > + > > + iommus: > > + maxItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - mediatek,gce-client-reg > > + - mediatek,gce-events > > + - power-domains > > + - clocks > > + - iommus > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/mt8183-clk.h> > > + #include <dt-bindings/gce/mt8183-gce.h> > > + #include <dt-bindings/power/mt8183-power.h> > > + #include <dt-bindings/memory/mt8183-larb-port.h> > > + > > + mdp3_wdma: mdp3-wdma@14006000 { > > + compatible = "mediatek,mt8183-mdp3-wdma"; > > + reg = <0x14006000 0x1000>; > > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 > > 0x1000>; > > + mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>, > > + <CMDQ_EVENT_MDP_WDMA0_EOF>; > > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > > + clocks = <&mmsys CLK_MM_MDP_WDMA0>; > > + iommus = <&iommu>; > > + };
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml new file mode 100644 index 000000000000..10786d769750 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek color correction + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com> + +description: | + MediaTek color correction with 3X3 matrix. + +properties: + compatible: + items: + - enum: + - mediatek,mt8183-mdp3-ccorr + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + description: The register of client driver can be configured by gce with + 4 arguments defined in this property. Each GCE subsys id is mapping to + a client defined in the header include/dt-bindings/gce/<chip>-gce.h. + + mediatek,gce-events: + description: + The event id which is mapping to the specific hardware event signal + to gce. The event id is defined in the gce header + include/dt-bindings/gce/<chip>-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/uint32-array + + clocks: + minItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - mediatek,gce-events + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8183-clk.h> + #include <dt-bindings/gce/mt8183-gce.h> + + mdp3_ccorr: mdp3-ccorr@1401c000 { + compatible = "mediatek,mt8183-mdp3-ccorr"; + reg = <0x1401c000 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>, + <CMDQ_EVENT_MDP_CCORR_EOF>; + clocks = <&mmsys CLK_MM_MDP_CCORR>; + }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml new file mode 100644 index 000000000000..95ec19543945 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,wdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Write Direct Memory Access + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + - Ping-Hsun Wu <ping-hsun.wu@mediatek.com> + +description: | + MediaTek Write Direct Memory Access(WDMA) component used to write + the data into DMA. + +properties: + compatible: + items: + - enum: + - mediatek,mt8183-mdp3-wdma + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + description: The register of client driver can be configured by gce with + 4 arguments defined in this property. Each GCE subsys id is mapping to + a client defined in the header include/dt-bindings/gce/<chip>-gce.h. + + mediatek,gce-events: + description: + The event id which is mapping to the specific hardware event signal + to gce. The event id is defined in the gce header + include/dt-bindings/gce/<chip>-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/uint32-array + + power-domains: + maxItems: 1 + + clocks: + minItems: 1 + + iommus: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - mediatek,gce-events + - power-domains + - clocks + - iommus + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8183-clk.h> + #include <dt-bindings/gce/mt8183-gce.h> + #include <dt-bindings/power/mt8183-power.h> + #include <dt-bindings/memory/mt8183-larb-port.h> + + mdp3_wdma: mdp3-wdma@14006000 { + compatible = "mediatek,mt8183-mdp3-wdma"; + reg = <0x14006000 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>, + <CMDQ_EVENT_MDP_WDMA0_EOF>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WDMA0>; + iommus = <&iommu>; + };