| Message ID | 20220824035542.706433-4-nava.kishore.manne@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add afi config drivers support | expand |
Use subject prefixes matching the subsystem (git log --oneline -- ...). "bindings" is no correct. On 24/08/2022 06:55, Nava kishore Manne wrote: > Updates binding document for the zynqmp afi config node to handle the > PS_PL Bus-width and resets. Use imperative language: https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95 > > Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com> > --- > .../bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml > index f14f7b454f07..9504665cad95 100644 > --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml > +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml > @@ -59,6 +59,13 @@ properties: > controller. > type: object > > + zynqmp-fpga: Just: fpga > + $ref: /schemas/fpga/xlnx,zynqmp-afi-fpga.yaml# > + description: The Zynq UltraScale+ MPSoC Processing System core provides > + access from PL masters to PS internal peripherals, and memory through > + AXI FIFO interface(AFI) > + type: object > + > required: > - compatible > Best regards, Krzysztof
Hi Krzysztof, Please find my response inline. > -----Original Message----- > From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Sent: Wednesday, August 24, 2022 6:28 PM > To: Manne, Nava kishore <nava.kishore.manne@amd.com>; git (AMD-Xilinx) > <git@amd.com>; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; > michal.simek@xilinx.com; mdf@kernel.org; hao.wu@intel.com; > yilun.xu@intel.com; trix@redhat.com; p.zabel@pengutronix.de; > gregkh@linuxfoundation.org; ronak.jain@xilinx.com; rajan.vaja@xilinx.com; > abhyuday.godhasara@xilinx.com; piyush.mehta@xilinx.com; > lakshmi.sai.krishna.potthuri@xilinx.com; harsha.harsha@xilinx.com; > linus.walleij@linaro.org; nava.manne@xilinx.com; > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org; linux-fpga@vger.kernel.org > Subject: Re: [PATCH 3/4] bindings: firmware: Update binding doc for the > zynqmp afi config node > > Use subject prefixes matching the subsystem (git log --oneline -- ...). > > "bindings" is no correct. Will fix in v2. > > On 24/08/2022 06:55, Nava kishore Manne wrote: > > Updates binding document for the zynqmp afi config node to handle the > > PS_PL Bus-width and resets. > > Use imperative language: > https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/sub > mitting-patches.rst#L95 Will fix in v2. > > > > Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com> > > --- > > .../bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp- > firmwa > > re.yaml > > b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp- > firmwa > > re.yaml index f14f7b454f07..9504665cad95 100644 > > --- > > a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp- > firmwa > > re.yaml > > +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-fi > > +++ rmware.yaml > > @@ -59,6 +59,13 @@ properties: > > controller. > > type: object > > > > + zynqmp-fpga: > > Just: fpga > Will fix in v2. Regards, Navakishore.
diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml index f14f7b454f07..9504665cad95 100644 --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml @@ -59,6 +59,13 @@ properties: controller. type: object + zynqmp-fpga: + $ref: /schemas/fpga/xlnx,zynqmp-afi-fpga.yaml# + description: The Zynq UltraScale+ MPSoC Processing System core provides + access from PL masters to PS internal peripherals, and memory through + AXI FIFO interface(AFI) + type: object + required: - compatible
Updates binding document for the zynqmp afi config node to handle the PS_PL Bus-width and resets. Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com> --- .../bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml | 7 +++++++ 1 file changed, 7 insertions(+)