Message ID | 20220819120649.21523-1-allen-kh.cheng@mediatek.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v3] dt-bindings: pinctrl: mt8186: Fix 'reg-names' for pinctrl nodes | expand |
On Fri, Aug 19, 2022 at 2:06 PM Allen-KH Cheng <allen-kh.cheng@mediatek.com> wrote: > The mt8186 contains 8 GPIO physical address bases that correspond to > the 'reg-names' of the pinctrl driver. The 'reg-names' entries in > bindings are ordered incorrectly, though. The system crashes due of an > erroneous address when the regulator initializes. > > We fix the 'reg-names' for the pinctrl nodes and the pinctrl-mt8186 > example in bindings. > > Fixes: 338e953f1bd1 ("dt-bindings: pinctrl: mt8186: add pinctrl file and binding document") > Co-developed-by: Guodong Liu <guodong.liu@mediatek.com> > Signed-off-by: Guodong Liu <guodong.liu@mediatek.com> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Reviewed-by: NĂcolas F. R. A. Prado <nfraprado@collabora.com> > --- > Change in v2: > * Remove changes of the formatting of addresses and add C-d-b tag for > Guodong This v2 patch applied! Yours, Linus Walleij
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml index 1eeb885ce0c6..26573a793b57 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml @@ -41,12 +41,12 @@ properties: Gpio base register names. items: - const: iocfg0 - - const: iocfg_bm - - const: iocfg_bl - - const: iocfg_br + - const: iocfg_lt - const: iocfg_lm + - const: iocfg_lb + - const: iocfg_bl - const: iocfg_rb - - const: iocfg_tl + - const: iocfg_rt - const: eint interrupt-controller: true @@ -235,9 +235,9 @@ examples: <0x10002A00 0x0200>, <0x10002c00 0x0200>, <0x1000b000 0x1000>; - reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", - "iocfg_br", "iocfg_lm", "iocfg_rb", - "iocfg_tl", "eint"; + reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", + "iocfg_lb", "iocfg_bl", "iocfg_rb", + "iocfg_rt", "eint"; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pio 0 0 185>;