| Message ID | 20220608083553.8697-3-tinghan.shen@mediatek.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | Add support for MT8195 SCP 2nd core | expand |
Hi Tinghan, I have started reviewing this set and I expect comments to be spread out over a few days. I will tell you when I am done. Please see below for comments... On Wed, Jun 08, 2022 at 04:35:46PM +0800, Tinghan Shen wrote: > MT8195 SCP is a dual-core processor. The SCP core 1 watchdog timeout > interrupt uses the same interrupt line of SCP core 0 watchdog timeout > interrupt. > > Add support for handling SCP core 1 watchdog timeout interrupt in the > SCP IRQ handler. > > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> > --- > drivers/remoteproc/mtk_common.h | 4 ++++ > drivers/remoteproc/mtk_scp.c | 27 ++++++++++++++++++++++++++- > 2 files changed, 30 insertions(+), 1 deletion(-) > > diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h > index ea6fa1100a00..73e8adf00de3 100644 > --- a/drivers/remoteproc/mtk_common.h > +++ b/drivers/remoteproc/mtk_common.h > @@ -54,6 +54,10 @@ > #define MT8192_CORE0_WDT_IRQ 0x10030 > #define MT8192_CORE0_WDT_CFG 0x10034 > > +#define MT8195_SYS_STATUS 0x4004 > +#define MT8195_CORE0_WDT BIT(16) > +#define MT8195_CORE1_WDT BIT(17) > + > #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) > > #define SCP_FW_VER_LEN 32 > diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c > index 47b2a40e1b4a..3510c6d0bbc8 100644 > --- a/drivers/remoteproc/mtk_scp.c > +++ b/drivers/remoteproc/mtk_scp.c > @@ -212,6 +212,31 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp) > } > } > > +static void mt8195_scp_irq_handler(struct mtk_scp *scp) > +{ > + u32 scp_to_host; > + > + scp_to_host = readl(scp->reg_base + MT8192_SCP2APMCU_IPC_SET); > + > + if (scp_to_host & MT8192_SCP_IPC_INT_BIT) { > + scp_ipi_handler(scp); > + > + /* > + * SCP won't send another interrupt until we clear > + * MT8192_SCP2APMCU_IPC. > + */ > + writel(MT8192_SCP_IPC_INT_BIT, > + scp->reg_base + MT8192_SCP2APMCU_IPC_CLR); > + } else { > + if (readl(scp->reg_base + MT8195_SYS_STATUS) & MT8195_CORE1_WDT) { > + writel(1, scp->reg_base + MT8195_CORE1_WDT_IRQ); > + } else { > + writel(1, scp->reg_base + MT8192_CORE0_WDT_IRQ); > + scp_wdt_handler(scp, scp_to_host); Why is scp_wdt_handler() not called when CORE1 signals a watchdog failure? If this is the intended behaviour there is no way for anyone but you to know that it is the case. > + } > + } > +} > + > static irqreturn_t scp_irq_handler(int irq, void *priv) > { > struct mtk_scp *scp = priv; > @@ -961,7 +986,7 @@ static const struct mtk_scp_of_data mt8192_of_data = { > static const struct mtk_scp_of_data mt8195_of_data = { > .scp_clk_get = mt8195_scp_clk_get, > .scp_before_load = mt8195_scp_before_load, > - .scp_irq_handler = mt8192_scp_irq_handler, > + .scp_irq_handler = mt8195_scp_irq_handler, > .scp_reset_assert = mt8192_scp_reset_assert, > .scp_reset_deassert = mt8192_scp_reset_deassert, > .scp_stop = mt8195_scp_stop, > -- > 2.18.0 >
Hi Mathieu, > Hi Tinghan, > > I have started reviewing this set and I expect comments to be spread out over a few > days. I will tell you when I am done. > > Please see below for comments... > > On Wed, Jun 08, 2022 at 04:35:46PM +0800, Tinghan Shen wrote: > > MT8195 SCP is a dual-core processor. The SCP core 1 watchdog timeout > > interrupt uses the same interrupt line of SCP core 0 watchdog timeout > > interrupt. > > > > Add support for handling SCP core 1 watchdog timeout interrupt in the > > SCP IRQ handler. > > > > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> > > --- > > drivers/remoteproc/mtk_common.h | 4 ++++ > > drivers/remoteproc/mtk_scp.c | 27 ++++++++++++++++++++++++++- > > 2 files changed, 30 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h > > index ea6fa1100a00..73e8adf00de3 100644 > > --- a/drivers/remoteproc/mtk_common.h > > +++ b/drivers/remoteproc/mtk_common.h > > @@ -54,6 +54,10 @@ > > #define MT8192_CORE0_WDT_IRQ 0x10030 > > #define MT8192_CORE0_WDT_CFG 0x10034 > > > > +#define MT8195_SYS_STATUS 0x4004 > > +#define MT8195_CORE0_WDT BIT(16) > > +#define MT8195_CORE1_WDT BIT(17) > > + > > #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) > > > > #define SCP_FW_VER_LEN 32 > > diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c > > index 47b2a40e1b4a..3510c6d0bbc8 100644 > > --- a/drivers/remoteproc/mtk_scp.c > > +++ b/drivers/remoteproc/mtk_scp.c > > @@ -212,6 +212,31 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp) > > } > > } > > > > +static void mt8195_scp_irq_handler(struct mtk_scp *scp) > > +{ > > + u32 scp_to_host; > > + > > + scp_to_host = readl(scp->reg_base + MT8192_SCP2APMCU_IPC_SET); > > + > > + if (scp_to_host & MT8192_SCP_IPC_INT_BIT) { > > + scp_ipi_handler(scp); > > + > > + /* > > + * SCP won't send another interrupt until we clear > > + * MT8192_SCP2APMCU_IPC. > > + */ > > + writel(MT8192_SCP_IPC_INT_BIT, > > + scp->reg_base + MT8192_SCP2APMCU_IPC_CLR); > > + } else { > > + if (readl(scp->reg_base + MT8195_SYS_STATUS) & MT8195_CORE1_WDT) { > > + writel(1, scp->reg_base + MT8195_CORE1_WDT_IRQ); > > + } else { > > + writel(1, scp->reg_base + MT8192_CORE0_WDT_IRQ); > > + scp_wdt_handler(scp, scp_to_host); > > Why is scp_wdt_handler() not called when CORE1 signals a watchdog failure? If > this is the intended behaviour there is no way for anyone but you to know that > it is the case. It's becuase the handler of CORE1 timeout doesn't exist at this patch. The CORE1 timeout handler is added at patch 7 of this series. You're right. This makes people confused. I'll combine this patch with the CORE1 timeout handler. Best regards, TingHan
diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index ea6fa1100a00..73e8adf00de3 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -54,6 +54,10 @@ #define MT8192_CORE0_WDT_IRQ 0x10030 #define MT8192_CORE0_WDT_CFG 0x10034 +#define MT8195_SYS_STATUS 0x4004 +#define MT8195_CORE0_WDT BIT(16) +#define MT8195_CORE1_WDT BIT(17) + #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) #define SCP_FW_VER_LEN 32 diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 47b2a40e1b4a..3510c6d0bbc8 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -212,6 +212,31 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp) } } +static void mt8195_scp_irq_handler(struct mtk_scp *scp) +{ + u32 scp_to_host; + + scp_to_host = readl(scp->reg_base + MT8192_SCP2APMCU_IPC_SET); + + if (scp_to_host & MT8192_SCP_IPC_INT_BIT) { + scp_ipi_handler(scp); + + /* + * SCP won't send another interrupt until we clear + * MT8192_SCP2APMCU_IPC. + */ + writel(MT8192_SCP_IPC_INT_BIT, + scp->reg_base + MT8192_SCP2APMCU_IPC_CLR); + } else { + if (readl(scp->reg_base + MT8195_SYS_STATUS) & MT8195_CORE1_WDT) { + writel(1, scp->reg_base + MT8195_CORE1_WDT_IRQ); + } else { + writel(1, scp->reg_base + MT8192_CORE0_WDT_IRQ); + scp_wdt_handler(scp, scp_to_host); + } + } +} + static irqreturn_t scp_irq_handler(int irq, void *priv) { struct mtk_scp *scp = priv; @@ -961,7 +986,7 @@ static const struct mtk_scp_of_data mt8192_of_data = { static const struct mtk_scp_of_data mt8195_of_data = { .scp_clk_get = mt8195_scp_clk_get, .scp_before_load = mt8195_scp_before_load, - .scp_irq_handler = mt8192_scp_irq_handler, + .scp_irq_handler = mt8195_scp_irq_handler, .scp_reset_assert = mt8192_scp_reset_assert, .scp_reset_deassert = mt8192_scp_reset_deassert, .scp_stop = mt8195_scp_stop,
MT8195 SCP is a dual-core processor. The SCP core 1 watchdog timeout interrupt uses the same interrupt line of SCP core 0 watchdog timeout interrupt. Add support for handling SCP core 1 watchdog timeout interrupt in the SCP IRQ handler. Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> --- drivers/remoteproc/mtk_common.h | 4 ++++ drivers/remoteproc/mtk_scp.c | 27 ++++++++++++++++++++++++++- 2 files changed, 30 insertions(+), 1 deletion(-)