mbox series

[0/4] Add afi config drivers support

Message ID 20220824035542.706433-1-nava.kishore.manne@amd.com (mailing list archive)
Headers show
Series Add afi config drivers support | expand

Message

Manne, Nava kishore Aug. 24, 2022, 3:55 a.m. UTC 
Xilinx SoC platforms (Zynq and ZynqMP) connect the PS to the programmable
logic (PL) through the AXI port.This AXI port helps to establish the data
path between the PS and PL. In-order to establish the proper communication
data path between PS and PL the AXI port data path should be configured
with the proper Bus-width values and it will also handle the PS-PL reset
signals to reset the PL domain.

This patch series adds afi config drivers support to handle the PS-PL
resets and AXI port bus-width configurations.

Nava kishore Manne (4):
  firmware: xilinx: Add afi ioctl support
  bindings: fpga: Add binding doc for the zynqmp afi config driver
  bindings: firmware: Update binding doc for the zynqmp afi config node
  fpga: zynqmp: Add afi config driver

 .../firmware/xilinx/xlnx,zynqmp-firmware.yaml |   7 +
 .../bindings/fpga/xlnx,zynqmp-afi-fpga.yaml   | 100 +++++++++
 MAINTAINERS                                   |   6 +
 drivers/firmware/xilinx/zynqmp.c              |  14 ++
 drivers/fpga/Kconfig                          |  13 ++
 drivers/fpga/Makefile                         |   1 +
 drivers/fpga/zynqmp-afi.c                     | 211 ++++++++++++++++++
 include/linux/firmware/xlnx-zynqmp.h          |  36 +++
 8 files changed, 388 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
 create mode 100644 drivers/fpga/zynqmp-afi.c

Comments

Xu Yilun Aug. 27, 2022, 6:02 a.m. UTC | #1 
On 2022-08-24 at 09:25:38 +0530, Nava kishore Manne wrote:
> Xilinx SoC platforms (Zynq and ZynqMP) connect the PS to the programmable

Could you help explain what is PS?

Thanks,
Yiljn

> logic (PL) through the AXI port.This AXI port helps to establish the data
> path between the PS and PL. In-order to establish the proper communication
> data path between PS and PL the AXI port data path should be configured
> with the proper Bus-width values and it will also handle the PS-PL reset
> signals to reset the PL domain.
> 
> This patch series adds afi config drivers support to handle the PS-PL
> resets and AXI port bus-width configurations.
> 
> Nava kishore Manne (4):
>   firmware: xilinx: Add afi ioctl support
>   bindings: fpga: Add binding doc for the zynqmp afi config driver
>   bindings: firmware: Update binding doc for the zynqmp afi config node
>   fpga: zynqmp: Add afi config driver
> 
>  .../firmware/xilinx/xlnx,zynqmp-firmware.yaml |   7 +
>  .../bindings/fpga/xlnx,zynqmp-afi-fpga.yaml   | 100 +++++++++
>  MAINTAINERS                                   |   6 +
>  drivers/firmware/xilinx/zynqmp.c              |  14 ++
>  drivers/fpga/Kconfig                          |  13 ++
>  drivers/fpga/Makefile                         |   1 +
>  drivers/fpga/zynqmp-afi.c                     | 211 ++++++++++++++++++
>  include/linux/firmware/xlnx-zynqmp.h          |  36 +++
>  8 files changed, 388 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml
>  create mode 100644 drivers/fpga/zynqmp-afi.c
> 
> -- 
> 2.25.1
>
Manne, Nava kishore Aug. 30, 2022, 6:05 a.m. UTC | #2 
Hi Yilun,

	Please find my response inline.

> -----Original Message-----
> From: Xu Yilun <yilun.xu@intel.com>
> Sent: Saturday, August 27, 2022 11:33 AM
> To: Manne, Nava kishore <nava.kishore.manne@amd.com>
> Cc: git (AMD-Xilinx) <git@amd.com>; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; michal.simek@xilinx.com;
> mdf@kernel.org; hao.wu@intel.com; trix@redhat.com;
> p.zabel@pengutronix.de; gregkh@linuxfoundation.org;
> ronak.jain@xilinx.com; rajan.vaja@xilinx.com;
> abhyuday.godhasara@xilinx.com; piyush.mehta@xilinx.com;
> lakshmi.sai.krishna.potthuri@xilinx.com; harsha.harsha@xilinx.com;
> linus.walleij@linaro.org; nava.manne@xilinx.com;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> kernel@vger.kernel.org; linux-fpga@vger.kernel.org
> Subject: Re: [PATCH 0/4]Add afi config drivers support
> 
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> 
> On 2022-08-24 at 09:25:38 +0530, Nava kishore Manne wrote:
> > Xilinx SoC platforms (Zynq and ZynqMP) connect the PS to the
> > programmable
> 
> Could you help explain what is PS?
> 

The Zynq UltraScale MPSoC family consists of a system-on-chip (SoC) style integrated processing system (PS)
and a Programmable Logic (PL) unit, providing an extensible and flexible SoC solution on a single die.

Will add PS description in next version.

Regards,
Navakishore.