| Message ID | 20220823093221.38075-2-likexu@tencent.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | x86/pmu: Corner cases fixes and optimization | expand |
On Tue, Aug 23, 2022, Like Xu wrote: > From: Like Xu <likexu@tencent.com> > > When a guest PEBS counter is cross-mapped by a host counter, software > will remove the corresponding bit in the arr[global_ctrl].guest and > expect hardware to perform a change of state "from enable to disable" > via the msr_slot[] switch during the vmx transaction. > > The real world is that if user adjust the counter overflow value small > enough, it still opens a tiny race window for the previously PEBS-enabled > counter to write cross-mapped PEBS records into the guest's PEBS buffer, > when arr[global_ctrl].guest has been prioritised (switch_msr_special stuff) > to switch into the enabled state, while the arr[pebs_enable].guest has not. > > Close this window by clearing invalid bits in the arr[global_ctrl].guest. > > Fixes: 854250329c02 ("KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations") > Signed-off-by: Like Xu <likexu@tencent.com> > --- > arch/x86/events/intel/core.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c > index 2db93498ff71..75cdd11ab014 100644 > --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -4052,8 +4052,9 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) > /* Disable guest PEBS if host PEBS is enabled. */ > arr[pebs_enable].guest = 0; > } else { > - /* Disable guest PEBS for cross-mapped PEBS counters. */ > + /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */ > arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask; > + arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask; > /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */ > arr[global_ctrl].guest |= arr[pebs_enable].guest; > } Please post this as a separate patch to the perf folks (Cc: kvm@).
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 2db93498ff71..75cdd11ab014 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -4052,8 +4052,9 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data) /* Disable guest PEBS if host PEBS is enabled. */ arr[pebs_enable].guest = 0; } else { - /* Disable guest PEBS for cross-mapped PEBS counters. */ + /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */ arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask; + arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask; /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */ arr[global_ctrl].guest |= arr[pebs_enable].guest; }