| Message ID | 20220826182803.604563-6-paul.kocialkowski@bootlin.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Allwinner A31/A83T MIPI CSI-2 and A31 ISP / Platform Support | expand |
Hi Paul, Thank you for the patch. On Fri, Aug 26, 2022 at 08:28:02PM +0200, Paul Kocialkowski wrote: > MIPI CSI-2 is supported on the A83T with a dedicated controller that > covers both the protocol and D-PHY. It can be connected to the CSI > interface as a V4L2 subdev through the fwnode graph. > > This is not done by default since connecting the bridge without a > subdev attached to it will cause a failure on the CSI driver. No urgency, but would it be possible to fix this so that the CSI-2 receiver can be connected to the CSI unconditionally in DT ? The connection exists at the hardware level in the SoC, and should thus exist here too, regardless of whether or not a sensor is connected. > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> > --- > arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi > index 82fdb04122ca..ecf9f3b2c0c0 100644 > --- a/arch/arm/boot/dts/sun8i-a83t.dtsi > +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi > @@ -1064,6 +1064,32 @@ csi: camera@1cb0000 { > status = "disabled"; > }; > > + mipi_csi2: csi@1cb1000 { > + compatible = "allwinner,sun8i-a83t-mipi-csi2"; > + reg = <0x01cb1000 0x1000>; > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_CSI>, > + <&ccu CLK_CSI_SCLK>, > + <&ccu CLK_MIPI_CSI>, > + <&ccu CLK_CSI_MISC>; > + clock-names = "bus", "mod", "mipi", "misc"; > + resets = <&ccu RST_BUS_CSI>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + mipi_csi2_in: port@0 { > + reg = <0>; > + }; > + > + mipi_csi2_out: port@1 { > + reg = <1>; > + }; > + }; > + }; > + > hdmi: hdmi@1ee0000 { > compatible = "allwinner,sun8i-a83t-dw-hdmi"; > reg = <0x01ee0000 0x10000>;
Hi Laurent, On Fri 26 Aug 22, 21:59, Laurent Pinchart wrote: > Hi Paul, > > Thank you for the patch. > > On Fri, Aug 26, 2022 at 08:28:02PM +0200, Paul Kocialkowski wrote: > > MIPI CSI-2 is supported on the A83T with a dedicated controller that > > covers both the protocol and D-PHY. It can be connected to the CSI > > interface as a V4L2 subdev through the fwnode graph. > > > > This is not done by default since connecting the bridge without a > > subdev attached to it will cause a failure on the CSI driver. > > No urgency, but would it be possible to fix this so that the CSI-2 > receiver can be connected to the CSI unconditionally in DT ? The > connection exists at the hardware level in the SoC, and should thus > exist here too, regardless of whether or not a sensor is connected. Yes it's true that having the link always would be legitimate. For the context, this CSI controller can be switched between the MIPI CSI-2 controller and a parallel sensor input (i.e. it's not dedicated to one or the other like on the V3). Last time I tried, having the connection between the two always there resulted in the unability to use a parallel sensor when no sensor is attached to the mipi csi-2 receiver. Probably because the async notifier never completes since the mipi csi-2's subdev is never registered without a sensor subdev attached. Do you see a way to handle this case properly? Thanks, Paul > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> > > --- > > arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++++++++++++++++++++++++++ > > 1 file changed, 26 insertions(+) > > > > diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi > > index 82fdb04122ca..ecf9f3b2c0c0 100644 > > --- a/arch/arm/boot/dts/sun8i-a83t.dtsi > > +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi > > @@ -1064,6 +1064,32 @@ csi: camera@1cb0000 { > > status = "disabled"; > > }; > > > > + mipi_csi2: csi@1cb1000 { > > + compatible = "allwinner,sun8i-a83t-mipi-csi2"; > > + reg = <0x01cb1000 0x1000>; > > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_CSI>, > > + <&ccu CLK_CSI_SCLK>, > > + <&ccu CLK_MIPI_CSI>, > > + <&ccu CLK_CSI_MISC>; > > + clock-names = "bus", "mod", "mipi", "misc"; > > + resets = <&ccu RST_BUS_CSI>; > > + status = "disabled"; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + mipi_csi2_in: port@0 { > > + reg = <0>; > > + }; > > + > > + mipi_csi2_out: port@1 { > > + reg = <1>; > > + }; > > + }; > > + }; > > + > > hdmi: hdmi@1ee0000 { > > compatible = "allwinner,sun8i-a83t-dw-hdmi"; > > reg = <0x01ee0000 0x10000>; > > -- > Regards, > > Laurent Pinchart
On Thu, Sep 01, 2022 at 04:04:40PM +0200, Paul Kocialkowski wrote: > Hi Laurent, > > On Fri 26 Aug 22, 21:59, Laurent Pinchart wrote: > > Hi Paul, > > > > Thank you for the patch. > > > > On Fri, Aug 26, 2022 at 08:28:02PM +0200, Paul Kocialkowski wrote: > > > MIPI CSI-2 is supported on the A83T with a dedicated controller that > > > covers both the protocol and D-PHY. It can be connected to the CSI > > > interface as a V4L2 subdev through the fwnode graph. > > > > > > This is not done by default since connecting the bridge without a > > > subdev attached to it will cause a failure on the CSI driver. > > > > No urgency, but would it be possible to fix this so that the CSI-2 > > receiver can be connected to the CSI unconditionally in DT ? The > > connection exists at the hardware level in the SoC, and should thus > > exist here too, regardless of whether or not a sensor is connected. > > Yes it's true that having the link always would be legitimate. > > For the context, this CSI controller can be switched between the MIPI CSI-2 > controller and a parallel sensor input (i.e. it's not dedicated to one or the > other like on the V3). > > Last time I tried, having the connection between the two always there resulted > in the unability to use a parallel sensor when no sensor is attached to the > mipi csi-2 receiver. Probably because the async notifier never completes since > the mipi csi-2's subdev is never registered without a sensor subdev attached. > > Do you see a way to handle this case properly? It sounds like an issue in the CSI-2 receiver driver. If there's no input device attached to it, it should register its subdev directly, without its own async notifier. > > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> > > > --- > > > arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++++++++++++++++++++++++++ > > > 1 file changed, 26 insertions(+) > > > > > > diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi > > > index 82fdb04122ca..ecf9f3b2c0c0 100644 > > > --- a/arch/arm/boot/dts/sun8i-a83t.dtsi > > > +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi > > > @@ -1064,6 +1064,32 @@ csi: camera@1cb0000 { > > > status = "disabled"; > > > }; > > > > > > + mipi_csi2: csi@1cb1000 { > > > + compatible = "allwinner,sun8i-a83t-mipi-csi2"; > > > + reg = <0x01cb1000 0x1000>; > > > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&ccu CLK_BUS_CSI>, > > > + <&ccu CLK_CSI_SCLK>, > > > + <&ccu CLK_MIPI_CSI>, > > > + <&ccu CLK_CSI_MISC>; > > > + clock-names = "bus", "mod", "mipi", "misc"; > > > + resets = <&ccu RST_BUS_CSI>; > > > + status = "disabled"; > > > + > > > + ports { > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + mipi_csi2_in: port@0 { > > > + reg = <0>; > > > + }; > > > + > > > + mipi_csi2_out: port@1 { > > > + reg = <1>; > > > + }; > > > + }; > > > + }; > > > + > > > hdmi: hdmi@1ee0000 { > > > compatible = "allwinner,sun8i-a83t-dw-hdmi"; > > > reg = <0x01ee0000 0x10000>;
Hi Laurent, On Thu 01 Sep 22, 17:21, Laurent Pinchart wrote: > On Thu, Sep 01, 2022 at 04:04:40PM +0200, Paul Kocialkowski wrote: > > Hi Laurent, > > > > On Fri 26 Aug 22, 21:59, Laurent Pinchart wrote: > > > Hi Paul, > > > > > > Thank you for the patch. > > > > > > On Fri, Aug 26, 2022 at 08:28:02PM +0200, Paul Kocialkowski wrote: > > > > MIPI CSI-2 is supported on the A83T with a dedicated controller that > > > > covers both the protocol and D-PHY. It can be connected to the CSI > > > > interface as a V4L2 subdev through the fwnode graph. > > > > > > > > This is not done by default since connecting the bridge without a > > > > subdev attached to it will cause a failure on the CSI driver. > > > > > > No urgency, but would it be possible to fix this so that the CSI-2 > > > receiver can be connected to the CSI unconditionally in DT ? The > > > connection exists at the hardware level in the SoC, and should thus > > > exist here too, regardless of whether or not a sensor is connected. > > > > Yes it's true that having the link always would be legitimate. > > > > For the context, this CSI controller can be switched between the MIPI CSI-2 > > controller and a parallel sensor input (i.e. it's not dedicated to one or the > > other like on the V3). > > > > Last time I tried, having the connection between the two always there resulted > > in the unability to use a parallel sensor when no sensor is attached to the > > mipi csi-2 receiver. Probably because the async notifier never completes since > > the mipi csi-2's subdev is never registered without a sensor subdev attached. > > > > Do you see a way to handle this case properly? > > It sounds like an issue in the CSI-2 receiver driver. If there's no > input device attached to it, it should register its subdev directly, > without its own async notifier. Yes it turns out there was an error on that side, thanks for bringing it up! I have sent a fixup series which takes care of it. Now it becomes possible to always describe the links without downsides. Well, the CSI driver will still wait for the MIPI CSI-2 bridge's subdev when its node is enabled in device-tree, but I think that is expected. Cheers, Paul > > > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> > > > > --- > > > > arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++++++++++++++++++++++++++ > > > > 1 file changed, 26 insertions(+) > > > > > > > > diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi > > > > index 82fdb04122ca..ecf9f3b2c0c0 100644 > > > > --- a/arch/arm/boot/dts/sun8i-a83t.dtsi > > > > +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi > > > > @@ -1064,6 +1064,32 @@ csi: camera@1cb0000 { > > > > status = "disabled"; > > > > }; > > > > > > > > + mipi_csi2: csi@1cb1000 { > > > > + compatible = "allwinner,sun8i-a83t-mipi-csi2"; > > > > + reg = <0x01cb1000 0x1000>; > > > > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > > > > + clocks = <&ccu CLK_BUS_CSI>, > > > > + <&ccu CLK_CSI_SCLK>, > > > > + <&ccu CLK_MIPI_CSI>, > > > > + <&ccu CLK_CSI_MISC>; > > > > + clock-names = "bus", "mod", "mipi", "misc"; > > > > + resets = <&ccu RST_BUS_CSI>; > > > > + status = "disabled"; > > > > + > > > > + ports { > > > > + #address-cells = <1>; > > > > + #size-cells = <0>; > > > > + > > > > + mipi_csi2_in: port@0 { > > > > + reg = <0>; > > > > + }; > > > > + > > > > + mipi_csi2_out: port@1 { > > > > + reg = <1>; > > > > + }; > > > > + }; > > > > + }; > > > > + > > > > hdmi: hdmi@1ee0000 { > > > > compatible = "allwinner,sun8i-a83t-dw-hdmi"; > > > > reg = <0x01ee0000 0x10000>; > > -- > Regards, > > Laurent Pinchart
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 82fdb04122ca..ecf9f3b2c0c0 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -1064,6 +1064,32 @@ csi: camera@1cb0000 { status = "disabled"; }; + mipi_csi2: csi@1cb1000 { + compatible = "allwinner,sun8i-a83t-mipi-csi2"; + reg = <0x01cb1000 0x1000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI_SCLK>, + <&ccu CLK_MIPI_CSI>, + <&ccu CLK_CSI_MISC>; + clock-names = "bus", "mod", "mipi", "misc"; + resets = <&ccu RST_BUS_CSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_in: port@0 { + reg = <0>; + }; + + mipi_csi2_out: port@1 { + reg = <1>; + }; + }; + }; + hdmi: hdmi@1ee0000 { compatible = "allwinner,sun8i-a83t-dw-hdmi"; reg = <0x01ee0000 0x10000>;
MIPI CSI-2 is supported on the A83T with a dedicated controller that covers both the protocol and D-PHY. It can be connected to the CSI interface as a V4L2 subdev through the fwnode graph. This is not done by default since connecting the bridge without a subdev attached to it will cause a failure on the CSI driver. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> --- arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)