| Message ID | 20220907155813.1427526-6-tomas.winkler@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | GSC support for XeHP SDV and DG2 | expand |
On 9/7/2022 8:58 AM, Tomas Winkler wrote: > From: Alexander Usyskin <alexander.usyskin@intel.com> > > Define GSC on XeHP SDV (Intel(R) dGPU without display) > > XeHP SDV uses the same hardware settings as DG1, but uses polling > instead of interrupts and runs the firmware in slow pace due to > hardware limitations. > > Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com> > Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> > Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> This is unchanged from the previously reviewed rev, so this still applies: Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Daniele > --- > drivers/gpu/drm/i915/gt/intel_gsc.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c > index 73498c2574c8..e1040c8f2fd3 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gsc.c > +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c > @@ -56,6 +56,19 @@ static const struct gsc_def gsc_def_dg1[] = { > } > }; > > +static const struct gsc_def gsc_def_xehpsdv[] = { > + { > + /* HECI1 not enabled on the device. */ > + }, > + { > + .name = "mei-gscfi", > + .bar = DG1_GSC_HECI2_BASE, > + .bar_size = GSC_BAR_LENGTH, > + .use_polling = true, > + .slow_firmware = true, > + } > +}; > + > static const struct gsc_def gsc_def_dg2[] = { > { > .name = "mei-gsc", > @@ -107,6 +120,8 @@ static void gsc_init_one(struct drm_i915_private *i915, > > if (IS_DG1(i915)) { > def = &gsc_def_dg1[intf_id]; > + } else if (IS_XEHPSDV(i915)) { > + def = &gsc_def_xehpsdv[intf_id]; > } else if (IS_DG2(i915)) { > def = &gsc_def_dg2[intf_id]; > } else {
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c index 73498c2574c8..e1040c8f2fd3 100644 --- a/drivers/gpu/drm/i915/gt/intel_gsc.c +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c @@ -56,6 +56,19 @@ static const struct gsc_def gsc_def_dg1[] = { } }; +static const struct gsc_def gsc_def_xehpsdv[] = { + { + /* HECI1 not enabled on the device. */ + }, + { + .name = "mei-gscfi", + .bar = DG1_GSC_HECI2_BASE, + .bar_size = GSC_BAR_LENGTH, + .use_polling = true, + .slow_firmware = true, + } +}; + static const struct gsc_def gsc_def_dg2[] = { { .name = "mei-gsc", @@ -107,6 +120,8 @@ static void gsc_init_one(struct drm_i915_private *i915, if (IS_DG1(i915)) { def = &gsc_def_dg1[intf_id]; + } else if (IS_XEHPSDV(i915)) { + def = &gsc_def_xehpsdv[intf_id]; } else if (IS_DG2(i915)) { def = &gsc_def_dg2[intf_id]; } else {